(Translated by https://www.hiragana.jp/)
https://library.oapen.org/handle/20.500.12657/41662 のHTMLバージョンです。
Googleではファイルを自動的じどうてきにHTMLに変換へんかんして保存ほぞんしています。
ハイライトされているキーワード: semiconductor package
Semiconductor Packaging
Page 1
Semiconductor
Packaging
Andrea Chen
Randy Hsiao-Yu Lo
Semiconductor Packaging
Chen
Lo

Page 2
Semiconductor
Packaging
Materials
Interaction
and
Reliability

Page 3

Page 4
Semiconductor
Packaging
Andrea Chen
Randy Hsiao-Yu Lo
Materials
Interaction
and
Reliability
CRC Press is an imprint of the
Taylor & Francis Group, an informa business
Boca Raton London New York

Page 5
CRC Press
Taylor & Francis Group
6000 Broken Sound Parkway NW, Suite 300
Boca Raton, FL 33487-2742
© 2012 by Taylor & Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group, an Informa business
No claim to original U.S. Government works
Version Date: 20110819
International Standard Book Number-13: 978-1-4398-6207-0 (eBook - PDF)
This book contains information obtained from authentic and highly regarded sources. Reasonable
efforts have been made to publish reliable data and information, but the author and publisher cannot
assume responsibility for the validity of all materials or the consequences of their use. The authors and
publishers have attempted to trace the copyright holders of all material reproduced in this publication
and apologize to copyright holders if permission to publish in this form has not been obtained. If any
copyright material has not been acknowledged please write and let us know so we may rectify in any
future reprint.
Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced,
transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or
hereafter invented, including photocopying, microfilming, and recording, or in any information stor-
age or retrieval system, without written permission from the publishers.
For permission to photocopy or use material electronically from this work, please access www.copy-
right.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC), 222
Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that pro-
vides licenses and registration for a variety of users. For organizations that have been granted a pho-
tocopy license by the CCC, a separate system of payment has been arranged.
Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are
used only for identification and explanation without intent to infringe.
Visit the Taylor & Francis Web site at
http://www.taylorandfrancis.com
and the CRC Press Web site at
http://www.crcpress.com

Page 6
v
Contents
Preface.............................................................................................................. xiii
Authors...............................................................................................................xv
Partial.list.of.abbreviations,.acronyms,.and.symbols............................... xvii
Section I: Semiconductor packages
Chapter 1 History and background ........................................................... 3
1.1. Objectives................................................................................................... 3
1.2. Introduction............................................................................................... 3
1.3. Brief.history............................................................................................... 4
1.3.1. Hermetic.packaging................................................................... 4
1.3.2. Plastic.packaging........................................................................ 4
1.4. Wire.bonding.process.flow..................................................................... 5
1.5. Flip-chip.process.flow.comparison........................................................ 5
1.6. Equipment................................................................................................. 6
1.7. Material.interactions................................................................................ 6
Bibliography......................................................................................................... 9
Chapter 2 Package form factors and families ........................................ 11
2.1. Objectives................................................................................................. 11
2.2. Introduction............................................................................................. 11
2.3. Package.outline.standardization.......................................................... 11
2.4. Leaded.package.families....................................................................... 12
2.4.1. Dual.lead.package.family........................................................ 12
2.5. Quad.lead.package.family.................................................................... 13
2.6. Substrate-based.package.families........................................................ 13
2.6.1. Ball.grid.array.package.family............................................... 14
2.7. Chip.scale.packages............................................................................... 15
2.7.1. Substrate-based.chip.scale.packages..................................... 16
2.7.2. Quad.flat.no.lead...................................................................... 16
2.8. Stacked-die.package.family.................................................................. 17
2.9. Package-on-package.and.related.variations....................................... 17

Page 7
vi
Contents
2.10. Flip-chip.packages................................................................................. 18
2.11. Wafer-level.chip.scale.packages........................................................... 18
Bibliography....................................................................................................... 20
Chapter 3 Surface-mount technology ...................................................... 23
3.1. Objectives................................................................................................. 23
3.2. Introduction............................................................................................. 23
3.3. Background............................................................................................. 24
3.4. Package.cracking.or.“popcorning”...................................................... 27
3.5. Surface-mount.packages:.peripheral.leads.versus.area.array.......... 27
3.6. Issues.with.advanced.packaging......................................................... 29
3.7. Current.and.future.trends..................................................................... 30
3.7.1. Lead-free.and.halogen-free.packaging................................. 30
Bibliography....................................................................................................... 31
Chapter 4 Other packaging needs ............................................................ 33
4.1. Objectives................................................................................................. 33
4.2. Introduction............................................................................................. 33
4.3. Tape.automated.bonding....................................................................... 33
4.4. Micro.electro-mechanical.systems.(MEMS)....................................... 34
4.5. Image.sensor.modules........................................................................... 35
4.6. Memory.cards......................................................................................... 35
4.7. Packaging.needs.for.solar.technology................................................. 40
Bibliography....................................................................................................... 41
Section II: Package reliability
Chapter 5 Reliability testing ..................................................................... 45
5.1. Introduction............................................................................................. 45
5.2. Background............................................................................................. 46
5.3. Examples.of.reliability.tests.................................................................. 46
5.3.1. Preconditioning.conditions..................................................... 48
5.3.1.1. Package.failure.mode:.package.crack.or.
popcorning............................................................... 48
5.3.2. Temperature.cycling.and.thermal.shock.............................. 48
5.3.2.1. Package.failure.modes.from.temperature.
cycling.and.thermal.shock..................................... 54
5.3.2.2. Package.failure.mode:.delamination.................... 54
5.3.3. High-temperature.storage.life................................................ 55
5.3.3.1. Package.failure.mode:.intermetallics.................... 55
5.3.4. Temperature-humidity-bias.tests........................................... 55
5.3.4.1. Package.failure.mode:.corrosion........................... 55
5.4. Limitations.of.reliability.testing........................................................... 56
Bibliography....................................................................................................... 57

Page 8
Contents
vii
Section III: Materials used in semiconductor packaging
Chapter 6 Polymers ..................................................................................... 61
6.1. Molding.compounds.............................................................................. 61
6.1.1. Objectives................................................................................... 61
6.1.2. Introduction............................................................................... 61
6.1.3. Background............................................................................... 61
6.1.4. Newer.formulations................................................................. 64
6.1.4.1. Biphenyl..................................................................... 64
6.1.4.2. Multifunctional........................................................ 65
6.1.4.3. Aromatic.resins........................................................ 65
6.1.5. Technology.challenges............................................................. 66
6.1.5.1. Moldability............................................................... 66
6.1.5.2. Glass.transition.temperature................................. 67
6.1.5.3. Flexural.modulus..................................................... 67
6.1.5.4. Coefficient.of.thermal.expansion.......................... 68
6.1.5.5. Stress.index............................................................... 68
6.1.6. Failure.modes.associated.with.molding.compounds......... 69
6.1.6.1. Package.cracking.during.solder.reflow................ 69
6.1.6.2. Substrate.postmold.warpage................................. 71
6.1.7. Future.developments............................................................... 72
6.1.7.1. “Green”.molding.compounds.and.changes.
to.flame.retardant.additives................................... 72
6.1.7.2. Molded.underfill...................................................... 74
6.1.7.3. High-density.packaging......................................... 74
6.1.7.4. Compatibility.with.copper.wire.bonding............ 75
6.2. Die.attach.adhesives............................................................................... 75
6.2.1. Objectives................................................................................... 75
6.2.2. Introduction............................................................................... 76
6.2.3. Background............................................................................... 76
6.2.4. Materials.composition............................................................. 78
6.2.4.1. Liquid.epoxy.resin................................................... 78
6.2.4.2. Silver.flakes.and.other.filler.materials.................. 78
6.2.4.3. Reactive.epoxy.diluents.and.solvents................... 78
6.2.4.4. Catalysts.and.hardeners......................................... 78
6.2.4.5. Other.additives......................................................... 78
6.2.5. Materials.analysis..................................................................... 79
6.2.5.1. Glass.transition.temperature................................. 79
6.2.5.2. Coefficient.of.thermal.expansion.......................... 79
6.2.5.3. Thixotropic.index.................................................... 79
6.2.5.4. Ionic.purity............................................................... 80
6.2.6. Reliability.and.performance................................................... 81
6.2.6.1. Outgassing................................................................ 81
6.2.6.2. Resin.bleed................................................................ 81

Page 9
viii
Contents
6.2.7. Future.developments............................................................... 82
6.2.7.1. Three-dimensional.(3D).packaging...................... 82
6.2.7.2. Lead-free.and.restriction.of.hazardous.
substances.(RoHS)................................................... 83
6.2.7.3. Compatibility.with.copper.wire.bonding............ 83
6.2.7.4. Other.developments................................................ 84
6.3. Underfill.materials................................................................................. 84
6.3.1. Objectives................................................................................... 84
6.3.2. Introduction............................................................................... 84
6.3.3. What.is.underfill?..................................................................... 84
6.3.4. The.purpose.of.underfill......................................................... 84
6.3.5. The.(standard).underfill.process............................................ 85
6.3.6. Underfill.properties.................................................................. 86
6.3.6.1. Glass.transition.temperature................................. 87
6.3.6.2. Coefficient.of.thermal.expansion.......................... 87
6.3.7. Alternate.underfill.processes.................................................. 87
6.3.7.1. “No-flow”.underfill................................................. 87
6.3.7.2. Reworkable.underfill............................................... 88
6.3.7.3. Preapplied.underfill................................................ 88
6.3.7.4. Molded.underfill...................................................... 89
6.3.8. Areas.of.research.and.development...................................... 90
6.3.8.1. Maintaining.capillary.flow.as.features.sizes.
shrink........................................................................ 90
6.3.8.2. Compatibility.with.lead-free.bump.process.
steps,.including.for.copper.pillar.bumps............. 90
6.3.9. Failure.modes............................................................................ 90
6.4. Organic.substrates.................................................................................. 91
6.4.1. Objectives................................................................................... 91
6.4.2. Introduction............................................................................... 91
6.4.3. Background............................................................................... 91
6.4.4. Ball.grid.arrays.and.chip.scale.packages.............................. 92
6.4.4.1. Microvias.and.high-density.interconnect.
technology................................................................ 93
6.4.5. Future.developments............................................................... 94
Bibliography....................................................................................................... 97
Chapter 7 Metals ........................................................................................101
7.1. Lead.frames,.heat.spreaders,.and.heat.sinks.................................... 101
7.1.1. Objectives................................................................................. 101
7.1.2. Introduction............................................................................. 101
7.1.3. Lead.frames............................................................................. 101
7.1.4. Metals.commonly.used.in.lead.frames.and.other.
components............................................................................. 102
7.1.4.1. Copper..................................................................... 102

Page 10
Contents
ix
7.1.4.2. Alloy42.................................................................... 103
7.1.4.3. Aluminum.............................................................. 104
7.1.5. Heat.slugs,.heat.spreaders,.and.heat.sinks......................... 104
7.1.5.1. Heat.slugs.or.spreaders......................................... 104
7.1.5.2. Heat.sinks............................................................... 106
7.1.6. Plating.finishes....................................................................... 107
7.2. Bonding.wires....................................................................................... 107
7.2.1. Objectives................................................................................. 107
7.2.2. Introduction............................................................................. 107
7.2.3. Bonding.wires......................................................................... 108
7.2.3.1. Gold......................................................................... 108
7.2.3.2. Copper..................................................................... 108
7.2.3.3. Aluminum...............................................................110
7.2.3.4. Other.........................................................................110
7.2.4. Kirkendall.effect......................................................................111
7.2.4.1. Gold-aluminum.intermetallics.and.
Kirkendall.effect.....................................................111
7.2.4.2. Kirkendall.effect.for.copper.wire.bonding.
on.aluminum.bond.pads...................................... 112
7.2.5. Heat-affected.zone.phenomenon.in.bonding.wire............ 112
7.2.5.1. How.is.the.heat-affected.zone.created?...............113
7.2.5.2. Effect.of.heat-affected.zone.on.loop.height.........113
7.2.6. Other.reliability.issues............................................................113
7.2.6.1. Copper.wire.bonding.and.corrosion...................113
7.2.7. Materials.analysis....................................................................114
7.2.7.1. Visual.inspection....................................................115
7.2.7.2. Bond.etching...........................................................115
7.2.7.3. Bond.pull..................................................................115
7.2.7.4. Ball.shear.tests.........................................................115
7.2.8. Recent.developments..............................................................115
7.2.8.1. Copper.wire.bonding.on.nickel-palladium.
electroless.plated.bond.pads.................................116
7.3. Solders.....................................................................................................116
7.3.1. Objectives..................................................................................116
7.3.2. Introduction..............................................................................117
7.3.3. Types.of.solders.......................................................................117
7.3.3.1. Lead-based...............................................................117
7.3.3.2. Lead-free..................................................................118
7.3.3.3. Gold-based.............................................................. 120
7.4. Wafer.bumping..................................................................................... 121
7.4.1. Objectives................................................................................. 121
7.4.2. Introduction............................................................................. 121
7.4.3. Bump.metallurgies................................................................. 122
7.4.3.1. “C4”.......................................................................... 123

Page 11
x
Contents
7.4.3.2. Electroplating......................................................... 123
7.4.3.3. Electroless.(UBM).plating.and.screen/
stencil.printing.solder........................................... 125
7.4.3.4. Lead-free.bumping.metallurgies......................... 126
7.4.3.5. Alternative.to.solder.bumping.technologies..... 127
7.4.4. Under-bump.metallurgy....................................................... 127
7.4.4.1. Vacuum.deposition................................................ 128
7.4.4.2. Electroplating......................................................... 128
7.4.4.3. Electroless.plating.................................................. 128
7.4.5. Technical.issues...................................................................... 128
7.4.6. Future.directions.................................................................... 129
Bibliography..................................................................................................... 129
Chapter 8 Ceramics and glasses ............................................................. 133
8.1. Objectives............................................................................................... 133
8.2. Introduction........................................................................................... 133
8.3. Types.of.ceramics.used.in.semiconductor.packaging..................... 133
8.3.1. Alumina................................................................................... 135
8.3.2. Beryllia..................................................................................... 135
8.3.3. Aluminum.nitride.................................................................. 135
8.3.4. Silicon.carbide......................................................................... 136
8.3.5. Boron.nitride........................................................................... 137
8.4. Types.of.glasses.used.in.semiconductor.packaging........................ 137
8.4.1. Silver-filled.glass..................................................................... 139
8.4.2. Lead.alkali.borosilicate.glass................................................ 139
Bibliography..................................................................................................... 139
Section IV:—The future
Chapter 9 Trends and challenges ........................................................... 143
9.1. Objectives............................................................................................... 143
9.2. Introduction........................................................................................... 143
9.3. Copper.interconnects.and.low-κかっぱ.dielectric.materials..................... 143
9.3.1. Copper.interconnects............................................................. 143
9.3.2. Dielectric.materials................................................................ 145
9.4. Dielectric.constant.requirements.at.each.technology.node........... 146
9.5. Future.interconnect.and.dielectric.materials................................... 148
9.5.1. Interconnects.for.<22.nm....................................................... 148
9.5.2. Dielectric.materials.for.≥22.nm............................................ 150
9.5.3. Dielectric.materials.for.<22.nm............................................ 150
9.6. Future.packaging.options................................................................... 151
9.6.1. Codesigning.the.chip.with.the.package.............................. 151
9.6.2. Three-dimensional.(3D).integration.................................... 151

Page 12
Contents
xi
9.6.3. Through-silicon.vias.............................................................. 151
Bibliography..................................................................................................... 153
Chapter 10 Light-emitting diodes ............................................................ 155
10.1. Objectives............................................................................................... 155
10.2. Introduction........................................................................................... 155
10.3. Unique.characteristics.of.light-emitting.diode.(LED).
packaging.needs................................................................................... 157
10.4. Reliability.requirements.for.LED.packages...................................... 160
Bibliography......................................................................................................161
Glossary .......................................................................................................... 163
Bibliography..................................................................................................... 165
Appendix A: Analytical tools.......................................................................167
A.1. Introduction............................................................................................167
A.2. Types.of.analytical.tools.......................................................................167
A.3. Nondestructive.tools.and.tests........................................................... 168
A.3.1. Introduction............................................................................. 168
A.3.2. Optical/visual.inspection..................................................... 168
A.3.3. X-ray.inspection...................................................................... 168
A.3.4. Scanning.acoustic.microscopy............................................. 170
Bibliography......................................................................................................174
Appendix B: Destructive tools and tests................................................... 177
B.1. Introduction........................................................................................... 177
B.2. Decapsulation....................................................................................... 178
B.3. Dye.penetration.................................................................................... 178
B.4. Cross-sectioning.and.polishing......................................................... 178
B.5. Scanning.electron.microscopy.(SEM)................................................ 178
B.6. Transmission.electron.microscopy.(TEM)........................................ 179
B.7. Chemical.and.elemental.tests............................................................. 180
B.7.1. Auger.electron.spectroscopy.(AES)..................................... 180
B.7.2. Energy-dispersive.X-ray.spectroscopy.(EDS.or.EDX)....... 181
B.7.3. Fourier.transform.infrared.spectroscopy.(FTIR)............... 181
B.7.4. Secondary.ion.mass.spectrometry.(SIMS).......................... 183
B.8. Other.analytical.techniques................................................................ 183
B.8.1. Bonding.wire.pull.................................................................. 183
B.8.2. Ball.bond.shear....................................................................... 183
B.8.3. Differential.scanning.calorimetry.(DSC)............................ 184
B.8.4. Flexural.testing....................................................................... 184
Bibliography..................................................................................................... 186
Index................................................................................................................. 189

Page 13

Page 14
xiii
Preface
Semiconductor. packaging. assembly. and. testing. is. an. important. manu-
facturing.step.necessary.to.create.electronic.products..The.subject.is.not.
understood.in.much.depth,.as.compared.to.a.subject.like.circuit.design..It.
is.generally.believed.that.this.is.due.to.the.nature.of.the.topic,.as.back-end.
processing.of.semiconductors.is.a.multidisciplinary.area,.encompassing.
materials.science,.mechanical.design,.electrical.layout.and.modeling,.and.
many.other.engineering.specialties..This.book.specifically.addresses.that.
shortcoming,.especially.in.the.area.of.materials.used.for.packaging.semi-
conductors.and.their.interactions.
Simply.put,.semiconductor.packages.are.not.monolithic.entities.but.
are.made.up.of.many.different.components.interlocked.with.the.common.
goal.of.protecting.the.integrated.circuit.while.allowing.it.to.communi-
cate.with.the.outside.world—the.lead.frame.or.substrate.on.which.the.
chip.sits.upon,.the.die.attach.adhesive.to.glue.the.chip.down,.electrical.
connections. made. via. metallic. bonding. wires. or. bond. pad. bumps. for.
flip-chip.attachment,.and.finally.an.epoxy.molding.compound.to.encap-
sulate.everything.for.protection..And,.those.components.are.made.up.of.
very.different.materials:.polymers,.composites,.metals,.and.various.com-
binations.of.those.categories..Understanding.how.the.various.materials.
behave.and.interact.as.they.form.the.protective.barrier.for.the.delicate.
chip.is.key.for.making.the.package.reliable.and.robust.
To.gain.these.insights,.a.basic.knowledge.of.material.properties.is.nec-
essary,.along.with.determining.which.behaviors.are.important.to.package.
performance.. That. takes. understanding. how. a. given. property. is. mea-
sured.and.why.it.is.significant..For.example,.the.measurement.of.viscosity.
versus.time—a.viscosity.curve—in.a.molding.compound.or.the.length.
of.the.heat-affected.zone.in.metallic.wire.used.in.thermosonic.bonding.
eventually.translates.into.a.certain.level.of.performance.for.manufactur-
ing.or.reliability.purposes.for.a.given.package.
From.there,.the.next.step.is.looking.at.how.these.properties.of.various.
packaging.materials.interact.with.one.another.and.how.to.maximize.their.
performance.in.regard.to.package.integrity.and.reliability..Again,.as.an.
example,.the.length.of.the.heat-affected.zone.in.a.bonding.wire.will.help.

Page 15
xiv
Preface
determine.how.high.or.how.low.the.final.loop.height.will.be..In.another.
example,.a.viscosity.curve.for.a.molding.compound.often.acts.as.an.indi-
cator.of.its.utility.in.manufacturing,.by.its.ability.to.efficiently.and.com-
pletely.fill.cavities.in.a.mold.chase.
This.book.is.focused.on.providing.a.fundamental.understanding.of.
the.underlying.physical.properties.that.make.up.the.materials.used.in.a.
semiconductor.package..By.tying.together.the.disparate.elements.that.are.
essential. to. a. semiconductor. package,. this. volume. hopes. to. convey. the.
knowledge.of.how.all.the.parts.fit.and.work.together.to.provide.durable.
protection.to.the.integrated.circuit.chip.within.as.well.as.a.means.for.the.
chip.to.communicate.with.the.outside.world.

Page 16
xv
Authors
Andrea Chen.received.a.B.S..in.Materials.Science.and.Engineering.from.
University.of.California,.Berkeley.and.a.M.S..in.Materials.Engineering.
from.Rensselaer.Polytechnic.Institute,.New.York..She.started.her.career.at.
National.Semiconductor.Corporation.in.the.Package.Technology.group,.
working.on.various.semiconductor.packaging.materials.and.reliability.
issues.. Subsequently,. she. went. to. ChipPAC,. Inc.,. with. the. Technology.
Development.group,.involved.in.low-cost.flip-chip.technology.develop-
ment..Currently,.Chen.works.at.Siliconware.USA,.Inc..(SPIL).as.a.techni-
cal.marketing.manager..To.date,.she.has.coauthored.more.than.30.papers.
and.presentations.
Randy Hsiao-Yu Lo.received.his.B.S..from.National.Taiwan.University,.
Taiwan.in.1979;.M.S.from.Worcester.Polytechnic.Institute,.Massachusetts.
in. 1984;. and. Ph.D.. from. Purdue. University,. Indiana. in. 1990—all. in.
the. field. of. chemical. engineering.. He. was. at. National. Semiconductor.
Corporation. from. 1984. onward,. eventually. becoming. senior. engineer-
ing.manager.in.the.Package.Technology.group..Subsequently,.he.headed.
the.Electronic.Packaging.Development.group.at.ERSO/ITRI-Taiwan.from.
1997. to. 1998.. Then,. he. led. the. Siliconware. Precision. Industries. Limited.
(SPIL).Research.and.Development.group.until.2000..Later.that.same.year,.
he. was. appointed. executive. vice. president. and. head. of. North. America.
Sales.and.Marketing.for.Siliconware.USA,.Inc..In.2001,.Lo.was.appointed.
president.for.Siliconware.USA,.Inc.—the.position.he.currently.holds..To.
date,. he. has. coauthored. more. than. 20. papers. and. presentations. and. is.
listed.as.coinventor.on.over.30.U.S..patents.

Page 17

Page 18
xvii
Partial list of abbreviations,
acronyms, and symbols
ACLV—autoclave
AES—Auger.electron.spectroscopy
AlN—aluminum.nitride
Al2O3—alumina,.aluminum.oxide
ASIC—application-specific.integrated.circuit
CMOS—complementary.metal.oxide.semiconductor
CCD—charge.coupled.device
CSP—chip.scale.package
CTE—coefficient.of.thermal.expansion
DIP—dual.in-line.(through-hole.leads).package
DRAM—dynamic.random.access.memory
DSC—differential.scanning.calorimetry
DSP—digital.signal.processor
EFO—electronic.flame.off
EIA—Electronics.Industries.Alliance
EDS or EDX—energy-dispersive.X-ray.spectroscopy
ENIG—“Electroless.Nickel.Immersion.Gold”
ESD—electrostatic.discharge
FAB—free.air.ball
FPGA—field.programmable.gate.arrays
FTIR—Fourier.transform.infrared.spectroscopy
HAST—highly.accelerated.stress.test
HAZ—heat-affected.zone
HDI—high-density.interconnect
HTSL—high-temperature.storage.life
Hz—hertz,.as.in.one.cycle.per.second.(1.Hz.=.1.cycle.per.second)
IC—integrated.circuit
IQA—incoming.quality.assurance
I/O—input-output
IR—infrared
κかっぱ—dielectric.constant
LED—light-emitting.diode

Page 19
xviii
Partial list of abbreviations, acronyms, and symbols
LTCC—low-temperature.co-fired.ceramic
MCM—multichip.module
MCP—multichip.package
MEMS—Micro.Electro-Mechanical.System
OSP—organic.solderability.preservative
PCB—printed.circuit.board
PGA—(through-hole).pin.grid.array.packages
PLCC—plastic.leaded.chip.carriers,.with.surface-mount.J-leads
PoP—package-on-package
ppm—parts.per.million
PQFP—plastic.quad.flat.pack
PTH—plated.through-hole
RAM—random.access.memory
RGB—red-green-blue.(LED.lighting.combination)
SAM—scanning.acoustic.microscopy
SEM—scanning.electron.microscopy
SIMS—secondary.ion.mass.spectrometry
SiO2—silica,.silicon.dioxide
SO or SOP—small.outline.package,.with.gull-wing.surface-mount.leads
SOJ—small.outline.package,.but.with.surface-mount.J-leads
SMT—surface-mount.technology
TAB—tape.automated.bonding
TEM—transmission.electron.microscopy
Tg—glass.transition.temperature
THB—temperature-humidity-bias.reliability.test
TMCL—thermal.or.temperature.cycling.reliability.test
TOP—transistor.outline.package
TQFP—thin.quad.flat.pack
TSOP—thin.small.outline.package
YAG—ytterium-aluminum-garnet.(phosphor.used.in.LED.production)
Bibliography
C.A.. Harper,. Electronic Packaging and Interconnection Handbook,. McGraw-Hill.
Professional,.New.York,.1991.
L.T..Nguyen,.R.H.Y..Lo,.A.S..Chen,.and.J.G..Belani,.“Molding.Compound.Trends.in.
a.Denser.Packaging.World.II:.Qualification.Tests.and.Reliability.Concerns,”.
IEEE Trans. on Reliability,.vol..42,.no..4,.518–535,.December.1993.
S.L..Oon,.“The.Latest.LED.Technology.Improvement.in.Thermal.Characteristics.
and.Reliability—Avago.Technologies’.Moonstone.3-in-1.RGB.High.Power.
LED,”.Avago Technologies White Paper,.AV02-1752EN,.March.17,.2010.
M.. Wright,. “Intematix. Launches. New. Red. and. Green. LED. Phosphors,”. LEDs
Magazine,.November.11,.2010.

Page 20
section one
Semiconductor packages

Page 21

Page 22
3
chapter one
History and background
1.1 Objectives
•. Discover.semiconductor.packaging.
•. Provide. brief. background. and. history. of. semiconductor. packag-
ing.technology.
•. Learn. basic. process. steps. involved. in. plastic. semiconductor. pack-
age.assembly.
1.2 Introduction
Semiconductor.packaging.is.a.middle.link.in.electronics.systems.manu-
facturing,.starting.from.wafer.fabrication.of.multiple.integrated.circuits.
and.proceeding.all.the.way.to.final.enclosure.for.the.finished.product..It.
must.meet.the.demands.of.the.steps.prior.to.it,.at.the.front.end.of.produc-
tion,.and.those.steps.that.follow,.through.mounting.on.a.printed.circuit.
board.and.final.systems.integration..These.demands.tend.to.be.contradic-
tory,.while.at.the.same.time,.requirements.for.increased.and.better.perfor-
mance.from.the.package.are.always.increasing.
Simply.put,.a.semiconductor.package.is.a.semiconductor.chip.enclosed.
or.encapsulated.to.assure.environmental.protection,.and.it.provides.for.
a.reliable.means.of.interconnection.to.the.next.level.of.integration..The.
package.is.dubbed.the.first level.of.packaging,.with.the.circuit.board.being.
the.second level.and.the.final.enclosure.the.third level.
Specifically,. a. semiconductor. package. should. protect. the. chip. from.
mechanical. stresses. (vibration,. falling. from. a. height),. environmental.
stresses.(such.as.humidity.and.contaminants),.and.electrostatic.discharge.
(also.known.as.ESD).during.handling.and.mounting.onto.a.printed.circuit.
board.and.beyond..In.addition,.the.package.is.the.mechanical.interface.
for.electrical.testing,.burn-in,.and.the.next.level.of.interconnection..Last,.
the.package.must.also.meet.the.chip’s.various.performance.requirements,.
encompassing.the.physical,.mechanical,.electrical,.and.thermal..Finally,.
the.package.must.meet.specifications.for.quality.and.reliability.as.well.as.
be.a.cost-effective.solution.toward.the.final.product..In.all,.semiconduc-
tor.packages.are.an.important.part.of.any.electronics.system,.though.it.is.
often.neglected.or.treated.as.an.afterthought—until.there.is.a.problem.

Page 23
4
Semiconductor packaging: materials interaction and reliability
Therefore,.this.chapter.addresses.background.information.needed.to.
understand.the.use.and.importance.of.the.various.materials.and.compo-
nents.used.in.semiconductor.packaging.
1.3 Brief history
Here.is.a.brief.description.of.the.progression.of.semiconductor.packages,.
from.metal.cans.and.ceramic.packages.in.the.early.days.to.today’s.pack-
ages.made.up.of.lightweight.organic.materials..In.the.future,.even.more.
exotic.materials.may.be.commonplace.in.complex.package.structures.
1.3.1 Hermetic packaging
As.already.mentioned,.in.the.early.days.of.the.semiconductor.industry,.
the.majority,.if.not.all,.of.semiconductor.packages.were.ceramic.based.or.
metal.cans..Given.that.the.earliest.adopters.of.semiconductors.were.the.
military.and.aerospace.industries,.hermetic.packages.offered.the.highest.
levels.of.reliability.under.any.possible.adverse.operating.conditions..By.
design,. a. hermetic. seal. prevents. any. contaminants,. whether. gases,. liq-
uids,.or.particulates,.from.reaching.the.sensitive.and.relatively.delicate.
semiconductor. chip. surface. within. the. package. cavity.. More. details. on.
hermetic.packages.are.given.in.Chapter.2.
However,. their. robustness. also. had. drawbacks.. Hermetic. materials.
tend.to.be.costly.and.hard.to.manufacture.and.process,.due.to.their.hard-
ness. and. brittle. natures.. The. packages—the. ceramic. ones,. especially—
could. be. heavy. and. large,. which. meant. the. printed. circuit. board. and.
overall.enclosure.had.to.also.be.large.and.heavy.to.support.the.weight..
Finally,.hermetic.packages.tend.not.to.lend.themselves.to.miniaturization..
The.semiconductor.industry.eventually.turned.to.using.organic.materials.
and.plastics,.for.both.cost.and.weight.savings,.starting.in.the.1970s.
Though.plastic.package.unit.volumes.now.far.surpass.those.for.hermetic.
ones,.they.remain.in.use.for.applications.that.have.demanding.performance.
and.environmental.needs..Two.applications.where.hermetic.packaging.still.
finds.demand.are.light-emitting.diode.(LED).and.Micro.Electro-Mechanical.
System.(MEMS).packaging,.which.is.discussed.in.Chapter.4.
Many.of.the.well-known.and.commonly.used.semiconductor.pack-
ages. that. will. be. described. shortly. have. both. ceramic. originators. and.
organic.successors..They.include.dual.in-line,.pin.grid.arrays,.leaded.chip.
carriers,.and.they.all.have.ceramic.and.molding.compound.versions.
1.3.2 Plastic packaging
The.plastic.version.of.the.dual.in-line.packaging.(DIP).family.was.intro-
duced.in.the.early.1970s.and.then.proceeded.to.dominate.the.market.for.

Page 24
Chapter one: History and background
5
plastic. packages. until. the. late. 1980s,. when. surface-mount. technology.
(SMT).arrived.on.the.scene,.with.quad.flat.packs,.small.outline.packages,.
and.plastic.leaded.chip.carriers.
To.summarize.the.progress.of.package.technology,.through-hole.pack-
ages.like.DIPs.were.the.first.plastic.semiconductor.packages.to.enter.wide-
spread. use.. “Through-hole”. refers. to. the. fact. the. package. leads. or. pins.
went.through.holes.in.the.printed.circuit.board.to.make.their.physical.and.
electrical.connections..Packages.and.their.leads.were.both.rather.large.in.
size..The.next.shift.in.technology.came.with.the.development.of.surface-
mount.technology,.where.the.package.leads.were.connected.to.lands.on.the.
circuit.board,.which.allowed.for.both.package.body.size.and.the.leads.to.
shrink.in.size..This.is.discussed.in.more.detail.in.Chapter.3..More.recently,.
the.increasing.pin.counts.forced.the.development.of.area.array.packages,.
like.the.ball.grid.array.(BGA)..The.trend.to.ever-smaller,.lighter,.and.thin-
ner.consumer.electronic.products.was.only.achievable.by.further.minia-
turization,. which. drove. the. concept. of. chip. scale. packaging. (CSP).. The.
next.step.to.reduce.packaging.cost.and.size.was.the.approach.of.finishing.
the.chip.package.directly.on.the.wafer;.thus,.wafer-level.packaging.(WLP).
was.created..Going.forward,.this.book.will.focus.on.plastic.semiconductor.
packages.grouped.by.interconnect.method,.whether.by.wire.bonding.or.
flip-chip.attachment,.and.finally.under.wafer-level.packaging.
Though.in.the.past,.packaging.and.interconnection.technologies.were.
not.limiting.factors.in.wringing.maximum.performance.out.of.a.device,.
demands.from.both.the.device.and.system.ends.has.meant.more.and.more.
focus.is.being.placed.on.package.technology.as.a.limiting.factor,.and.the.
industry.is.looking.for.ways.to.address.these.issues.
1.4 Wire bonding process flow
The.fundamental.process.flow.for.semiconductor.packaging.using.wire.
bonding. has. remained. relatively. unchanged. for. the. past. 40. and. more.
years,.though.the.equipment.and.materials.used.have.undergone.consid-
erable. improvement. and. changes.. Manufacturing. operations. have. gone.
from.manual,.labor-intensive.operations.to.highly.automated,.high-volume.
production..Materials.are.of.higher.overall.quality.and.chemical.purity,.
and.they.are.engineered.for.specific.properties.and.applications..Table 1.1.
shows.the.process.steps.associated.with.wire-bonded.packages,.both.plas-
tic.(such.as.for.a.plastic.ball.grid.array).and.hermetic.(such.as.for.ceramic.
dual-inline.packages).types,.and.Figure 1.1.illustrates.the.process.flow.
1.5 Flip-chip process flow comparison
Table 1.2.compares.the.process.steps.changes.going.from.a.wire-bonded.
substrate. package. to. one. using. a. flip. chip.. In. addition. to. starting. with.

Page 25
6
Semiconductor packaging: materials interaction and reliability
a.bumped.wafer,.the.major.changes.come.in.during.the.interconnection.
steps—die.attach.adhesive.plus.wire.bond.replaced.pick-and-place.plus.
reflow..Type.of.encapsulation.is.also.different,.with.molding.compound.
generally.replaced.by.underfill.
Further. discussion. on. underfill. materials. is. given. in. Chapter. 6,.
Section.6.3,.and.more.information.on.wafer.bumping.will.be.presented.in.
Chapter.7,.Section.7.4.
1.6 Equipment
As.an.example,.Figure 1.2.illustrates.a.transfer.mold.press.used.with.mold-
ing.compound.to.encapsulate.plastic.packages..Nearly.all.the.steps.shown.in.
Table 1.2,.which.describe.semiconductor.package.assembly.and.manufactur-
ing,.now.use.automated.equipment.for.volume.production—the.die.bonder,.
the.wafer.saw,.and,.of.course,.the.wire.bonder,.to.name.a.few.examples.
1.7 Material interactions
The.heterogeneous.components.that.make.up.a.semiconductor.package.
often.differ.wildly.in.physical.properties,.as.shown.in.Table 1.3..The.key.
is.to.find.the.most.reasonable.material.set.that.is.also.cost-effective.and.
manufacturable.in.high-volume.assembly..These.interactions.will.be.dis-
cussed.in.detail.in.subsequent.chapters.
Table 1.1  Comparison.of.Process.Steps.between.Package.Types
Plastic (Lead Frame)
Plastic (Laminate)
Hermetic
Wafer.sort
Wafer.sort
Wafer.sort
Second.optical
Second.optical
Second.optical
Wafer.mount
Wafer.mount
Wafer.mount
Wafer.sawing
Wafer.sawing
Wafer.sawing
Die.attach
Die.attach
Die.attach
Wire.bond
Wire.bond
Wire.bond
Third.optical
Third.optical
Third.optical
Encapsulate.(molding.
compound)
Encapsulate.(molding.compound.or.
glob.top)
Lid.seal
Dejunk
Ball.attach.and.reflow
Leakage.test
Deflash
Singulate
Marking
Marking
Ball.inspection
Plating
Marking
Trim.and.form
Final.inspection
Final.inspection
Final.inspection
Source: Adapted. from. National. Semiconductor. Corporation,. Data Sheet: Semiconductor
Packaging Assembly Technology,.August.1999.

Page 26
Chapter one: History and background
7
1. Start bond cycle
2. Descend to 1st bond,
with ball centered and
captured in capillary.
3. Ball bond
4. Ascend to top of loop.
5. Descend to 2nd bond;
trajectory controls
loop shape.
6. Second bond lead.
7. Second bond formed.
8. Rise to control tail
length and to fire
electronic flame off (EFO)
for next bond.
9. EFO fires to create next ball.
Figure 1.1  Process.steps.in.gold.thermosonic.wire.bonding.

Page 27
8
Semiconductor packaging: materials interaction and reliability
Table 1.2  Wire.Bond.versus.Flip-Chip.
Process.Flows.for.a.Substrate.Package
Wire Bond
Flip Chip
Wafer
Wafer
Dice
Wafer.bumping
Die.attach
Dice
Cure
Pick.and.place.plus.flux
Wire.bonding
Reflow
Encapsulate
Underfill.encapsulation
Ball.attach
Ball.attach
Mark
Mark
System.test
System.test
Source: .A dapted. from. P.. Elenius. and. L.. Levine,.
“Comparing. Flip-Chip. and. Wire-Bond.
Interconnection. Technologies,”. Chip Scale
Review,.81–87,.July/August.2000.
Fixed cross head
Hydraulic ram
Movable cross head
Top platen
Top mold chase
Bottom mold chase
Bottom platen
Mold location
Mold heaters
Figure 1.2  Transfer.mold.press.

Page 28
Chapter one: History and background
9
Bibliography
M.G.. Bevan. and. B.M.. Romenesko,. “Modern. Electronic. Packaging. Technology,”.
Johns Hopkins APL Technical Digest,.vol..20,.no..1,.22–33,.1999.
P..Elenius.and.L..Levine,.“Comparing.Flip-Chip.and.Wire-Bond.Interconnection.
Technologies,”.Chip.Scale.Review,.81–87,.July/August.2000.
K..Gilleo,.B..Cotterman,.and.T..Chen,.“Molded.Underfill.for.Flip.Chip.in.Package,”.
HDI Magazine,.June.2000.
C.A.. Harper,. Electronic Packaging and Interconnection Handbook,. McGraw-Hill.
Professional,.New.York,.Chapter.6,.1991.
National.Semiconductor.Corporation,.Data Sheet: Hermetic Packages,.August.1999.
National.Semiconductor.Corporation,.Data Sheet: Semiconductor Packaging Assembly
Technology,.August.1999.
M.. Osborne,. “A. Comprehensive. Study. of. Fine-Pitch. Bonding. Reveals. the.
Importance.of.Process.Control,”.Chip Scale Review,.March.2006.
M..Töpper,.“10th.Anniversay.Insights—A.Short.History.of.Wafer-Level.Packaging,”.
Advanced Packaging,.April.2002.
R.R..Tummala,.“Electronic.Packaging.Research.and.Education:.A.Model.for.the.21st.
Century,”.Johns Hopkins APL Technical Digest,.vol..20,.no..1,.111–121,.1999.
Table 1.3  Key.Properties.of.Semiconductor.Packaging.Materials
Material
CTE
(ppm/°C)
Density
(g/cm3)
Thermal
Conductivity
(W/m*K)
Electrical
Resistivity
(µΩ-cm)
Tensile
Strength
(GPa)
Melting
Point
(°C)
Silicon
2.8
2.4
150
N/A
N/A
1430
Molding.
Compound
18–65
1.9
0.67
N/A
N/A
165.(Tg)
Copper
16.5
8.96
395
1.67
0.25–
0.45
1083
Alloy42
4.3
N/A
15.9
N/A
0.64
1425
Gold
N/A
19.3
293
2.2
N/A
1064
Aluminum
23.8
2.80
235
2.7
83
660
Eutectic.
Tin-Lead.
Solder
23.0
8.4
50
N/A
N/A
183
Alumina
6.9
3.6
22
N/A
N/A
2050
Aluminum.
nitride
4.6
3.3
170
N/A
N/A
2000
Source: .A dapted. from. National. Semiconductor. Corporation,. Data Sheet: Semiconductor
Packaging Assembly Technology,.August.1999.

Page 29

Page 30
11
chapter two
Package form factors and families
2.1 Objectives
•. List.and.categorize.the.different.types.of.plastic.semiconductor.pack-
ages.currently.available.on.the.market.
•. Discuss. the. various. failure. modes. plastic. packages. are. subject. to,.
and.potential.remedies.
2.2 Introduction
The.variety.of.plastic.semiconductor.packages.available.in.the.industry.
only.continues.to.proliferate.over.time..Even.as.new.types.and.form.fac-
tors. come. into. being,. the. established. players. do. not. disappear. entirely,.
given. their. long,. reliable. history. and. cost-competitiveness. when. price.
and.not.performance.is.the.primary.factor.for.package.selection..Table 2.1.
shows.the.mature.package.families.of.dual.in-line,.small.outline,.and.thin.
small.outline.packages.still.account.for.over.40%.of.semiconductor.pack-
age.units.produced.worldwide.
The. increase. in. the. number. of. package. types. matches. the. growth.
seen.in.the.number.and.types.of.electronic.products.entering.into.com-
mon.use..There.are.an.ever-growing.number.of.new.applications.for.per-
sonal,.healthcare,.home,.automotive,.security,.and.entertainment.systems..
Advancement.in.package.technology.helped.create.the.innovative.solu-
tions.needed.in.new.and.future.products.
2.3 Package outline standardization
The. industry. association. JEDEC—formed. in. 1958. as. the. Joint. Electron.
Devices.Engineering.Council.and.now.officially.known.as.JEDEC Solid
State Technology Association—regulates. the. standards. and. drawings. for.
package.configurations,.outlines..JEDEC.is.the.standardization.arm.of.the
Electronics Industries Alliance (EIA) and.is.a.member.of.that.umbrella.orga-
nization..The.comprehensive.guide.to.all.registered.package.outlines.is.in.
Publication.95.(JEP95),.located.on.the.JEDEC.website.

Page 31
12
Semiconductor packaging: materials interaction and reliability
2.4 Leaded package families
As.noted.in.Chapter.1,.leaded.packages.have.been.used.in.the.industry.
for.decades..Even.though.the.styles.of.packages.have.proliferated,.they.
remain.in.wide.use,.especially.for.low-pin.count.parts.and.when.cost.is.a.
primary.consideration.
2.4.1 Dual lead package family
Dual.leaded.packages.are.based.on.mature.two-sided.lead.frame.tech-
nology.utilizing.either.PTH.(plated.through.hole).or.SMT.(surface-mount.
technology)..Within.SMT.grouping,.there.is.J lead,.which.folds.underneath.
the.package.body,.and.gull wing,.where.the.leads.fan.away.from.the.pack-
age.body—configurations.available.for.different.SMT.requirements..Lead.
counts.range.up.to.86.pins.
Table 2.1  2007.Worldwide.Integrated.Circuit.(IC).
Packaging.Units.by.Package.Family
Package Type
Share, %
SO
24.8
TSOP
13.4
SOT
7.6
DIP
5.3
DCA
7.7
WLP
4.2
FBGA/DSBGA
13.7
BGA
4.4
PGA
0.1
QFN
5.4
QFP
9.2
CC
0.8
DFN
3.5
Total
100
151.billion.units
Notes: SO,. small. outline. package;. TSOP,. thin. small. outline.
package;. SOT,. small. outline. transistor;. DIP,. dual. in-
line. (through-hole. leads). package;. DCA,. direct. chip.
attach;.WLP,.wafer-level.packaging;.FBGA,.fine.pitch.
ball. grid. array/DSBGA,. die-sized. ball. grid. array;.
BGA,.ball.grid.array;.PGA,.pin.grid.array.packages;.
QFN,.quad.flat.no.lead;.QFP,.quad.flat.pack;.CC,.chip.
carrier;.DFN,.dual.flat.no.lead.
Source: Adapted. from. Sandra. Winkler,. “Trends. in. IC.
Packaging. and. Multicomponent. Packaging,”. IEEE
SCV Components, Packaging and Manufacturing
Technology Chapter,.January.22,.2009.

Page 32
Chapter two: Package form factors and families
13
There.are.a.multitude.of.package.types.within.the.dual.lead.family,.
depending.on.lead.type.and.shape,.lead.pitch,.and.body.size.and.thick-
ness..The.plastic.dual.in-line.package.(or.PDIP).uses.PTH.board.mounting.
technology..Of.the.dual.lead.packages.utilizing.SMT,.they.are.all.varia-
tions.of.the.small.outline.package.(SOP),.with.the.acronyms.and.names.
changing.depending.on.whether.the.lead.configuration.is.a.J-lead.(SOJ),.
or.on.the.body.profile.and.lead.pitches.
2.5 Quad lead package family
Quad.leaded.packages.are.based.on.mature.four-sided.lead.frame.tech-
nology.utilizing.SMT.(surface-mount.technology)..Within.SMT.grouping,.
there. are.J-lead.and.gull-wing. lead. configurations. available. for. different.
SMT.requirements..Lead.counts.range.up.to.256.pins.
The.quad.packages.with.J-leads.are.generally.known.as.plastic.leaded.
chip.carrier.(PLCC).and.have.lead.counts.up.to.84..Those.with.gull-wing.
leads.are.known.as.quad.flat.pack.(QFP).packages..The.QFP.subgroup.has.
several.variations,.depending.on.body.thickness.and.lead.pitch,.with.lead.
counts.ranging.up.to.256..QFP.packages.are.also.available.with.thermal.
enhancement,.such.as.an.exposed.heat.spreader.
Figure 2.1.shows.a.J-lead.plastic.package.in.a.cross-sectional.view,.and.
Figure 2.2.is.of.a.gull-wing.leaded.plastic.package.
2.6 Substrate-based package families
At.some.point,.an.input/output.(I/O).limitation.was.met.with.lead-frame-
based. packages.. The. leads. could. only. be. made. so. narrow. before. they.
became. too. fragile. to. handle. during. the. assembly. processes. and. final.
trim-and-form.. To. achieve. greater. I/O. density. to. match. the. shrinking.
Figure 2.1  J-lead.leaded.plastic.package.(not.to.scale).
Figure 2.2  Gull-wing.leaded.plastic.package.(not.to.scale).

Page 33
14
Semiconductor packaging: materials interaction and reliability
geometries.of.the.chip,.packages.were.developed.to.mimic.printed.circuit.
boards.(PCBs),.where.denser.electrical.connections.and.routing.could.be.
met..Another.advance.was.multitier.wire.bonding,.to.allow.for.staggered.
bonding. lands. to. meet. finer. pitch. densities.. Finally,. the. use. of. organic.
substrates. would. allow. flip-chip. interconnect. technology. to. become.
low(er). cost. and. more. widely. available. for. many. different. applications.
and.devices.
2.6.1 Ball grid array package family
In.a.ball.grid.array.(BGA).package,.the.chip.is.mounted.to.the.top.surface.
of.a.printed.circuit.board-type.substrate.instead.of.a.metal.lead.frame..If.
the.interconnection.is.wire.bonding,.the.wires.are.connected.to.electrical.
traces.on.the.substrate..Flip-chip.interconnections.may.also.be.employed.
Compared.to.lead-frame.packages,.BGA.packages.offer.superior.elec-
trical.and.thermal.performance,.higher.interconnect.density,.and.excel-
lent.surface-mount.yields.for.high.pin.counts.(usually.above.256,.which.is.
generally.the.upper.limit.for.QFPs).
A.BGA.is.a.package.technology.that.employs.a.solder.ball.grid.array.
matrix.to.make.electrical.input.and.output.connections.to.a.printed.circuit.
board.. BGAs. offers. improved. electrical. and. thermal. operation. through.
multiple.routing.layers.such.as.ground.and.power.planes..The.package.
family. includes. cavity-up. and. cavity-down. designs. utilizing. advanced.
substrate.technologies,.as.well.as.optional.heat.spreaders.and.heat.sinks.
when.even.higher.thermal.dissipation.is.a.necessity.
BGA.packages.are.commonly.used.for.high-performance.applications.
such. as. microprocessors. or. controllers,. application-specific. integrated.
circuits.(ASICs),.digital.signal.processors.(DSPs),.gate.arrays,.and.mem-
ory. and. computer. chipsets.. A. thermally. enhanced. version. is. shown. in.
Heat spreader
Epoxy overmold
Solder balls
Bismaleimide Triazine (BT)
substrate
Chip
Figure 2.3  Thermally.enhanced.ball.grid.array.(not.to.scale).

Page 34
Chapter two: Package form factors and families
15
Figure 2.3,.and.Figure 2.4.shows.a.cavity-down.version.that.provides.both.
thermal.and.electrical.improvements.
Polyimide. tape. can. also. be. used. as. a. substrate. material.. The. tape.
requires.attachment.to.a.heat.spreader.for.support.as.well.as.improved.
thermal.performance..Drilling.through.the.tape.to.allow.solder.ball.con-
nection.to.the.heat.spreader.to.act.as.a.ground.plane.improves.the.electri-
cal.performance.further,.as.illustrated.in.Figure 2.5.
2.7 Chip scale packages
A. chip. scale. package. (CSP). is. defined. as. a. package. where. the. bare. die.
occupies.80%.or.more.of.the.package.area,.so.the.profile.can.be.a.near-
chip-size. package. outline.. Electrical. performance. is. enhanced. due. to.
shorter.interconnections..CSPs.may.utilize.lead.frames.or.substrates,.and.
the.substrates.may.be.rigid.or.flexible..The.packages.may.have.solder.balls.
or.simply.metalized.lands;.the.lead.frame.version.may.not.have.external.
leads,.as.in.a.quad.flat.no-lead.package.(see.below)..Also,.interconnects.
may.be.wire.bonds.or.flip.chip.(see.Section.2.10,.Flip-chip.packages).
Chip
Heat slug
Substrate
Solder balls
Encapsulant
Figure 2.4  Cavity-down,.thermally.enhanced.ball.grid.array.(not.to.scale).
Chip
Polyimide tape
substrate
Encapsulant
Solder balls
Gold bond wire
Heat slug
Figure 2.5  Ball.grid.array.using.polyimide.tape.substrate.(not.to.scale).

Page 35
16
Semiconductor packaging: materials interaction and reliability
2.7.1 Substrate-based chip scale packages
Essentially,. substrate-based. chip. scale. package. technology. is. based.
on.mature.BGA.technology.and.infrastructure,.scaled.down.to.small.
form. factors.. Chip. scale. packages. must. also. meet. design. guidelines.
and.rules.regarding.solder.ball.pitch.and.array.patterns,.as.provided.
by.JEDEC.
2.7.2 Quad flat no lead
A.quad.flat.no-lead.(abbreviated.as.QFN).package.is.a.plastic.encapsu-
lated.lead-frame-based.CSP.with.a.lead.pad.on.the.bottom.of.the.pack-
age.to.provide.electrical.interconnection.with.the.printed.circuit.board..
This.package.offers.a.small.form.factor.with.60%.size.reduction.compared.
with.conventional.QFP.packages..It.provides.good.electrical.performance.
due. to. the. short. electrical. path. in. the. inner. leads. and. wires.. Electrical.
performance.may.be.further.enhanced.by.using.a.flip.chip.to.shorten.the.
interconnect.path.even.further..The.package.also.provides.excellent.ther-
mal.performance.by.an.optional.exposed.die.pad.to.provide.an.efficient.
heat.path.soldered.on.the.circuit.board..This.small.and.light.package.with.
improved. thermal. and. electrical. performance. makes. QFNs. suitable. for.
portable.communication.and.consumer.products.
As.already.mentioned,.interconnects.may.be.made.with.wire.bond-
ing.or.with.a.flip.chip..An.example.of.the.wire.bond.type.is.shown.in.
Figure 2.6,.and.those.of.the.flip-chip.versions.are.shown.in.Figure 2.7.
Note.that.punch type.and.map type.refer.to.both.the.molding.method.
and.subsequent.singulation.techniques..QFN.packages.may.be.molded.
individually.and.then.punched.out.of.the.lead.frame.like.other,.tradi-
tional. lead-frame. packages.. Or,. an. array. of. individual. QFN. packages.
may.be.molded.as.one.large.package.and.singulated.subsequently.by.
sawing.
Chip
Gold bond wires
Lead frame
Molding compound
Figure 2.6  Wire-bonded.quad.flat.no.lead.(not.to.scale).

Page 36
Chapter two: Package form factors and families
17
2.8 Stacked-die package family
The.stacked-die.package.is.a.package.technology.that.stacks.multiple.die.
vertically.in.the.same.package..For.example,.multiple.memory.devices.may.
sit.on.top.of.one.another.to.increase.memory.density,.or.ASICs.may.be.com-
bined.with.memory.chips..Compared.to.single-die.packages,.stacked-die.
packages.combine.several.different.functional.devices.or.increase.memory.
density.in.the.same.footprints.as.a.single-die.package..Stacked-die.pack-
ages.may.include.substrate-based.and.lead-frame-based.types.
2.9 Package-on-package and related variations
Multiple-package. packages. provide. an. alternative. to. multichip. module.
solutions.when.known-good-die.is.not.feasible..Multiple.chips.are.inte-
grated. individually. after. undergoing. functional. tests. within. one. pack-
age.form.factor..Rework.of.package.on.substrate.is.feasible.to.ensure.the.
module.yield..Figure 2.8.shows.a.variation.on.the.multiple-packages-in-
one.called.package-on-package,.or.PoP..In.this.example,.the.PoP.vertically.
combines.discrete.memory.(the.top.package).and.logic.chip.(the.bottom.
half).packages.to.save.board.space,.lower.overall.pin.count,.and.enhance.
electrical.performance.
Chip
Flip-chip bumps
Lead frame
Molding compound
Figure 2.7  Flip-chip.quad.flat.no.lead.(not.to.scale).
Figure 2.8  Package-on-package.(not.to.scale).

Page 37
18
Semiconductor packaging: materials interaction and reliability
2.10 Flip-chip packages
Flip-chip.packages.are.not.so.much.a.stand-alone.package.form.factor.
as.a.certain.set.of.packages.that.share.a.common.interconnect.character-
istic..Namely,.the.chip.is.not.wire.bonded.for.interconnect.but.instead.
flipped. face-to-face. with. the. substrate. surface—hence. the. name. flip
chip—and. the. interconnection. between. the. die. and. substrate. is. made.
through.an.array.of.bumps.that.are.placed.on.the.bonding.pads.of.the.
die.surface.
Flip-chip.packages.provide.a.solution.for.low.to.high.pin.count,.high.
electrical.performance.demands.from.high-end.memory,.ASICs,.and.micro-
processor.applications.where.high.frequency.and.high.speed.are.required..
Going.from.wire.bonding.to.a.flip-chip.configuration.makes.it.possible.to.
jump.into.a.higher.pin.count,.and.high.electrical.performance.applications.
Flip-chip. interconnections. allow. better. electrical. performance.
through.lower.inductances.due.to.the.shorter.electrical.path.between.the.
chip.and.the.substrate..The.array.of.bumps.under.the.chip.also.allows.the.
die.to.shrink.in.size,.which.can.reduce.wafer.cost..The.flip-chip.structure.
also.allows.you.to.make.power.and.ground.connections.to.internal.points.
on.a.die,.resulting.in.better.chip.performance..To.increase.thermal.per-
formance,.optional.heat.spreaders.can.be.attached.on.the.backside.of.the.
flipped.die.
Types.of.packages.employing.a.flip.chip.can.be.as.small.as.3.mm.on.a.
side.CSPs.up.to.mammoth.45.mm.on.a.side.BGAs..What.is.common.among.
all.of.them.is.the.need.for.enhanced.electrical.performance.by.shrinking.
the.bond.pad-to-lead.distance..This.can.be.seen.in.Figure 2.9,.which.shows.
the.improvement.in.return.loss.in.frequencies.below.9.GHz.between.a.
wire-bonded.quad.flat.no.lead.and.a.flip-chip.version..Figure 2.10.shows.
the.difference.in.insertion.loss,.which.shows.the.flip-chip.version.has.a.
bigger.bandwidth.range.given.that.the.wire.bonded.package.shows.1.dB.
insertion.loss.at.10.GHz.while.the.flip-chip.package.exhibits.that.behavior.
at.11.GHz.
2.11 Wafer-level chip scale packages
The. concept. of. wafer-level. packages. emerged. in. the. mid-1990s..
Figure  2.11. shows. a. cross. section. from. a. wafer-level. chip. scale. pack-
age.. Note. that. redistribution. is. used. to. reroute. connections. from. the.
peripheral. bond. pads. to. an. area. array. to. support. the. external. solder.
ball.connections.
A.simplified.process.flow.is.described.in.Table 2.2..A.finished.wafer.
would.undergo.subsequent.additional.processing.to.make.each.individual.
chip.a.package:.bond.pad.redistribution,.additional.layers.of.passivation,.
under.bump.metals,.and.finally.the.solder.ball.for.external.interconnection.

Page 38
Chapter two: Package form factors and families
19
0
–70
–60
–50
–40
R
etu
rn
L
o
ss (dB) –30
–20
–10
0
Return loss
FC-QFN
QFN
2
4
6
8
Frequency (GHz)
fcqfn.dat: S_I: S[port1:ml, port1:ml] (mag)
qfn.dat: S_I: S[port1:ml, port1:ml] (mag)
10
12
14
16
Figure 2.9  Return.loss.graphs.comparing.QFN.and.FC-QFN. (Reprinted.with.per-
mission.from.Kevin.Chang,.Jen-Yuan.Lai,.Hanping.Pu,.Yu-po.Wang,.C.S.Hsiao,.
Andrea. Chen,. and. Randy. H.Y.. Lo,. “Flip. Chip. Quad. Flat. No-Lead. (FC-QFN),”.
IWLPC 2005,.November.1,.2005.)
0
–10
–9
–8
–7
–6
Insertio
n
L
o
ss (dB) –3
–4
–5
–2
–1
0
Insertion loss
2
4
6
8
Frequency (GHz)
10
12
14
16
FC-QFN
QFN
fcqfn.dat: S_I: S[port1:ml, port3:ml] (mag)
qfn.dat: S_I: S[port1:ml, port3:ml] (mag)
Figure 2.10  Insertion.loss.graphs.comparing.QFN.and.FC-QFN..(Reprinted.with.
permission.from.Kevin.Chang,.Jen-Yuan.Lai,.Hanping.Pu,.Yu-po.Wang,.C.S.Hsiao,.
Andrea. Chen,. and. Randy. H.Y.. Lo,. “Flip. Chip. Quad. Flat. No-Lead. (FC-QFN),”.
IWLPC 2005,.November.1,.2005.)

Page 39
20
Semiconductor packaging: materials interaction and reliability
It.is.obvious.that.wafer-level.packaging.looks.similar.to.a.flip.chip,.
and.there.is.often.confusion.on.whether.a.bare.bumped.chip.is.a.wafer-
level.package.or.just.a.bare.flip.chip..Conventions.seem.to.dictate.that.a.
wafer-level.chip.scale.package.is.one.that.has.spherical.bumps.on.a.grid.
pattern. with. a. fixed,. predetermined. pitch,. whereas. as. a. bare. flip. chip.
would.not.adhere.to.these.rules.
Bibliography
M.G.. Bevan. and. B.M.. Romenesko,. “Modern. Electronic. Packaging. Technology,”.
Johns Hopkins APL Technical Digest,.vol..20,.no..1,.22–33,.1999.
K..Chang,.J.-Y..Lai,.H..Pu,.Y.-p..Wang,.C.S..Hsiao,.A..Chen,.and.R.H.Y..Lo,.“Flip.
Chip.Quad.Flat.No-Lead.(FC-QFN),”.IWLPC 2005,.November.1,.2005.
A..Chen,.E..Feng,.R..Lo,.C.-C..Wu,.T.D..Her,.and.C.Y..Lin,.“The.Future.in.3-D.Chip.
Scale.Packaging,”.SEMICON China 2002,.March.26–27,.2002.
A..Chen,.E..Feng,.R..Lo,.C.-C..Wu,.and.T.D..Her,.“Recent.Innovations.in.Stacked.
Die.Packages,”.KGD Workshop 2001,.September.12,.2001.
Freescale. Semiconductor,.Application Note: Quad Flat Pack No-Lead (QFN), Micro
Dual Flat Pack No-Lead (uDFN),.AN1902,.Rev..4.0,.September.2008.
UBM
Solder ball
RDL
PL1
PL2
Figure 2.11  Cross.section.of.a.wafer-level.chip.scale.package.(not.to.scale).
Table 2.2  Process.Flow.for.Wafer-Level.Chip.Scale.
Packages
Steps
Description
1
Finished.wafer.arrives.from.wafer.fabrication
2
Passivation.layer.1
3
Redistribution.of.bond.pads
4
Passivation.layer.2
5
Under.bump.metallurgy
6
Solder.bumping
7
Solder.bump.reflow

Page 40
Chapter two: Package form factors and families
21
C.A.. Harper,. Electronic Packaging and Interconnection Handbook,. McGraw-Hill.
Professional,.New.York,.Chapters.6.and.9,.1991.
M..Iyer,.“Emerging.Trends.in.Advanced.Packaging,”.Semiconductor International,.
June.1,.2009.
JEDEC,.JEP95: Publication 95,.www.jedec.org/download/pub95/default.cfm
JEDEC,. JEP95: Publication 95, Design Guide 4.18: Wafer Level Ball Grid Arrays
(WLBGA),.Issue.A,.September.2004.
JEDEC,. JEP95: Publication 95, Design Guide 4.6: Fine-Pitch, Rectangular Ball Grid
Array Package (FRBGA),.Issued,.April.2005.
JEDEC,.JEP156: Chip-Package Interaction—Understanding, Identification and Evaluation,.
March.2009.
R.H.Y..Lo.and.C.-C..Wu,.U.S..Patent.No..6,507,120:.Flip.Chip.Type.Quad.Flat.Non-
Leaded.Package,.January.14,.2003.
R..Mahajan,.K..Brown,.and.V..Atluri,.“The.Evolution.of.Microprocessor.Packaging,”.
Intel Technology Journal,.Q3,.1–10,.2000.
Maxim. Integrated. Products,. Application Note 4002: Understanding Flip-Chip and
Chip-Scale Package Technologies and Their Applications,.April.18,.2007.
National.Semiconductor,.Application Note 1126: BGA (Ball Grid Array),.August.2003.
P.J.C.. Normington,. “Patent. Review:. Patent. Illustrates. a. New. Use. for. Old.
Technology—Tape.Automated.Bonding,”.Chip Scale Review,.July.2003.
Siliconware.Precision.Industries.Ltd.,.www.spil.com.tw/
M..Töpper,.“10th.Anniversay.Insights—A.Short.History.of.Wafer-Level.Packaging,”.
Advanced Packaging,.April.2002.
S..Winkler,.“Trends.in.IC.Packaging.and.Multicomponent.Packaging,”.IEEE SCV
Components, Packaging and Manufacturing Technology Chapter,. January. 22,.
2009.

Page 41

Page 42
23
chapter three
Surface-mount technology
3.1 Objectives
•. Provide.a.brief.overview.of.semiconductor.packages.used.in.surface-
mount.technology.of.printed.circuit.boards.
•. Discuss. how. issues. particular. to. surface-mount. technology. affect.
semiconductor.packages.
•. Touch. upon. future. developments. in. the. area. of. surface-mount.
technology.
3.2 Introduction
Surface-mount.technology.(SMT).refers.to.how.various.semiconductors,.
passives,. and. other. components. are. attached. to. a. printed. circuit. board.
(PCB),.to.both.the.top.and.bottom.surfaces..In.the.beginning.of.the.elec-
tronics.industry,.both.packages.and.PCBs.were.relatively.large.in.scale..
Through-hole. packages. prevalent. in. the. early. days. were. called. that.
because.their.leads.fit.into.the.holes.drilled.through.the.PCBs.to.connect.
power,.ground,.and.circuitry.connections.
In. time,. the. demands. of. continual. miniaturization. of. electronic.
products.meant.the.boards.inside.them.had.to.shrink,.along.with.the.
chips.and.components..To.save.space.and.increase.device.density,.the.
much-smaller.lead.area.of.surface-mount.packages.supplanted.that.of.
through-hole. packages.. For. example,. the. lead. pitch. of. a. small. outline.
package.or.a.quad.flat.pack.is.half.that.or.more.compared.to.a.plastic.
dual.in-line.(through-hole).package,.at.1.27.mm.or.1.00.mm.versus.2.54.
mm.for.the.older.technology..And.not.just.for.semiconductors.but.also.
for.discrete.devices,.which.lost.their.axial.wire.leads.jutting.out.of.cylin-
drical. bodies. to. be. replaced. by. much-smaller. rectangular. bricks. with.
metalized.end.caps..Table 3.1.presents.a.comparison.of.package.types.
and.dimensions.
However,.the.transition.from.through-hole.mounting.technology.to.
surface.mount.proved.to.have.many.challenges,.not.the.least.of.which.was.
the.stress.imposed.on.the.semiconductor.packages,.to.the.point.their.reli-
ability.was.reduced.or.even.damaged..This.chapter.discusses.those.issues.
and.subsequent.solutions.developed.

Page 43
24
Semiconductor packaging: materials interaction and reliability
3.3 Background
One. major. stumbling. block. was. discovered. when. PCB. mounting. went.
from.through-hole.to.surface.mount,.in.the.solder.reflow.step..In.the.days.
of.through-hole.packages.and.mounting,.the.majority.of.components.were.
attached.to.one.side.of.the.board.and.the.PCBs.passed.through.a.wave.sol-
dering.machine,.where.molten.eutectic.tin-lead.(Sn-Pb).solder.was.pushed.
along.the.boards.backside,.to.wick.up.the.through-holes.to.weld.the.pack-
age.leads.to.the.board,.as.illustrated.in.Figure 3.1..Generally,.only.passive.
components.might.be.mounted.on.the.bottom.side.and.directly.exposed.
to. the. solder. wave,. as. the. general. wisdom. advised. not. exposing. active.
devices.to.molten.solder..Having.passive.components.only.on.the.bottom.
side.and.through-hole.active.components.is.now.generally.known.in.the.
industry.as.a.Type.III.SMT.assembly,.as.shown.in.Figure 3.2..And.while.the.
molten.metal.was.at.least.183°C—the.melting.point.for.eutectic.Sn-Pb.sol-
der—semiconductor.packages.unlikely.saw.peak.temperatures.very.close.
to.that.level,.insulated.as.they.were.by.the.thickness.of.the.PCB..So,.the.
thermal.stresses.experienced.by.the.components.were.relatively.benign.
Solder wave
PCB travel
Figure 3.1  Wave.soldering.through-hole.components.
Table 3.1  Comparison.of.Through-Hole.and.Surface-Mount.Package.Types
Package Type
Pin Pitch
Pin Length
Body
Thickness
Body Width
Plastic.dual.
in-line
2.54.mm
3.17.mm
4.06.mm
7.62.to.22.9.
mm
Small.outline
1.27.mm
0.76.mma
2.49.mm
3.94.to.7.62.
mm
Plastic.quad.
flat.pack
1.00.to.1.27.
mm
0.76.mm*
2.41.mm.and.
below
Variable
Source: .A dapted.from.Richard.D..Skinner,.Ed.,.Basic Integrated Circuit Technology Reference
Manual,. Integrated. Circuit. Engineering. Corporation,. Section. 3:. Packaging,. 1993,.
figure 3-10.
a. Solderable.length.

Page 44
Chapter three: Surface-mount technology
25
But. when. PCB. technology. moved. to. surface. mount,. a. number. of.
details.changed.in.the.solder.reflow.process..Table 3.2.shows.the.process.
steps.for.mixed.assemblies.of.through-hole.and.surface-mount.packages,.
also.illustrated.in.Figure 3.2.and.generally.referred.to.as.a.Type.II.SMT.
assembly..Boards.now.had.parts.mounted.on.both.sides,.so.it.was.more.
difficult.to.use.wave.soldering.as.an.attachment.process,.because.there.
are.few,.if.any,.through-holes.left..Also,.the.components.would.risk.being.
“washed”.off.by.the.molten.solder,.even.with.the.package.body.attached.
to. the. board. with. heat-resistant. adhesive.. Instead,. solder. reflow. would.
be. achieved. through. convection. heating,. at. first. through. vapor. phase.
ovens.and.nowadays.by.infrared.(IR).heat..The.process.flow.is.shown.in.
Table 3.3..This.also.meant.the.packages.would.experience.the.same.tem-
perature.excursions.as.the.leads.mounted.to.the.PCB..A.PCB.with.only.
SMT.components.is.called.a.Type.I.SMT.assembly.and.is.illustrated.in.
Figure 3.3..In.all,.the.thermal.stresses.on.the.components.and.packages.
increased.considerably.with.the.move.to.SMT.
Given.the.increased.thermal.stresses,.the.bill.of.materials.(BOM).that.
had.served.well.through-hole.mounting.began.to.fail.with.the.change.to.
Type II
Type III
Passive components
rough-hole
components
rough-hole
component
Passive components
Surface-mount
components
Figure  3.2  A. printed. circuit. board. populated. with. through-hole. and. surface-
mount.components.(Type.II.and.Type.III).

Page 45
26
Semiconductor packaging: materials interaction and reliability
Table 3.2  Typical.Attachment.Process.Flow.for.Mix.of.
Through-Hole.and.Surface-Mount.Components
1... Insert.leaded.components
2... Invert.printed.circuit.board
3... Apply.adhesive
4... Place.surface-mount.components
5... Cure.adhesive
6... Invert.board
7... Wave.solder
8... Clean.(if.necessary)
9... Electrical.test
Source: .A dapted. from. Intel. Corporation,. Intel® Manufacturing
Enabling Guide,.Chapter.1,.May.2010,.figure 1-2.
Table 3.3  Typical.Attachment.Process.Flow.for.Surface-
Mount.Components.Only
1... Screen.print.solder.paste.on.first.side
2... Place.components
3... Dry.solder.paste
4... Reflow.solder
(If.populating.a.double-sided.board,.continue.to.step.5..
Otherwise,.skip.to.step.10.)
5... Invert.printed.circuit.board
6... Screen.print.solder.paste.on.second.side
7... Place.components
8... Dry.solder.paste
9... Reflow.solder
10...Clean.(if.necessary)
11...Electrical.test
Source: .A dapted. from. Intel. Corporation,. Intel® Manufacturing
Enabling Guide,.Chapter.1,.May.2010,.figure 1-3.
Type I
Passive components
Surface-mount components
Figure 3.3  A. printed. circuit. board. populated. with. surface-mount. components.
only.(Type.I).

Page 46
Chapter three: Surface-mount technology
27
SMT..The.main.phenomenon.associated.with.the.change.is.called.package
cracking.and.was.nicknamed.popcorning.
3.4 Package cracking or “popcorning”
When.semiconductor.packages.were.relatively.small,.such.as.small.out-
line.packages,.the.changeover.to.SMT.did.not.unduly.stress.the.package.
integrity.. However,. when. large. and. thin. (3-mm. thickness. and. below).
surface-mount. packages. (such. as. quad. flat. packs. and. plastic. leaded.
chip.carriers,.and.later,.plastic.ball.grid.arrays).became.prevalent.in.the.
late.1980s,.the.phenomenon.nicknamed.popcorning.became.well.known..
Popcorning.occurs.when.a.moisture-filled.plastic.package.undergoes.the.
solder.reflow.process.in.an.in-line.oven..The.moisture.often.pools.in.areas.
of.weakened.adhesion,.which.eventually.causes.delamination..The.pack-
age.is.subjected.to.rapid.heating.to.temperatures.above.the.boiling.point.
of.water..Therefore,.the.moisture.inside.the.package.turns.to.steam.and.
exerts.pressure.to.escape..The.molding.compound.typically.cannot.with-
stand.the.force.and.commonly.fails.through.the.backside,.resulting.in.an.
external.crack..The.sound.of.the.package.failing.is.said.to.sound.like.pop-
corn.popping,.hence.the.term.popcorning..The.sequence.of.events.is.shown.
in.Figure 3.4.
A.standard—the.IPC-SM-786A—was.created.by.the.IPC.(the.Institute.
for. Interconnecting. and. Packaging. Electronic. Circuits). to. control. mois-
ture.levels.in.semiconductor.packages.prior.to.solder.reflow..The.specifi-
cation—now.superseded.by.J-STD-020.and.J-STD-032—specified.storage.
conditions,. the. need. for. dry-packing,. or. even. baking. before. reflow. for.
very.sensitive.packages.
Still,.there.was.great.interest.into.the.1990s.in.discovering.chemistries.
that.could.make.molding.compounds.that.were.less.moisture.sensitive..
Research.in.this.area.led.to.the.development.and.use.of.biphenyl-based.
molding. compounds. for. large. surface-mount. packages,. which. is. dis-
cussed.in.further.detail.in.Chapter.5,.Section.5.1.
3.5 S urface-mount packages: peripheral
leads versus area array
Another. difficulty. discovered. with. the. transition. from. through-hole. to.
SMT.is.that.the.leads.for.surface-mount.packages.are.more.delicate.and.
fragile.than.those.for.through-hole.packages..Again,.Table 3.1.shows.some.
dimensional.comparisons.with.a.plastic.quad.flat.pack—which.typically.
has. the. highest. density,. thinnest,. and. most. closely. spaced. leads. of. the.
surface-mount.packages—and.a.plastic.dual.in-line.package.

Page 47
28
Semiconductor packaging: materials interaction and reliability
Unfortunately,.the.number.of.I/O.(inputs.and.outputs).on.large.chips,.
like. microprocessors. and. field. programmable. gate. arrays. (or. FPGAs),.
continues.to.increase.with.time.and.the.lead.density.for.packages.with.
peripheral.leads.soon.reached.a.limit.of.about.300.leads..Above.that.num-
ber,.the.leads.were.simply.too.delicate.to.handle.in.high.volume.produc-
tion,.not.to.mention.the.increased.risk.of.solder.bridging.and.electrical.
shorts.from.the.closely.spaced.land.pads.
Enter.area.array.packages.to.fulfill.this.need,.particularly.the.ball.grid.
array.(BGA)..As.already.discussed.in.Chapter.2,.BGAs.were.developed.in.
the.early.1990s.and.are.descended.from.the.through-hole.pin.grid.arrays.
(PGAs).package.family..BGAs.appear.to.be.almost.miniature.PCBs,.with.
an.array.of.solder.bumps.spaced.by.a.given.fixed.pitch—hence,.the.word.
grid.in.the.package’s.name—on.the.bottom.side,.as.illustrated.in.Figure 3.5.
BGA. packages,. and. area. array. packages. in. general,. have. several.
advantages.over.surface-mount.packages.with.peripheral.leads,.beyond.
that.of.I/O.density..Other.advantages.include.shorter.electrical.connection.
distances.between.chip.and.main.PCB,.reducing.the.likelihood.of.unde-
sirable.electrical.characteristics.
Lead frame
Chip
Molding compound
Moisture saturation
Pressure swelling
Internal moisture vaporizes causing cracks
Vapor pocket
delamination
Cracks
Chip
Pressure released
Figure 3.4  Solder.reflow.package.cracking.sequence.of.events.

Page 48
Chapter three: Surface-mount technology
29
3.6 Issues with advanced packaging
The. development. of. new. and. innovative. package. form. factors. is. often.
accompanied.by.changes.and.difficulties.beyond.that.of.package.develop-
ment..As.most,.if.not.all,.of.the.new.package.types.coming.into.production.
use.surface-mount.technology,.that.is.one.of.the.hurdles.on.the.way.to.
market.acceptance.and.volume.production.
One.example.of.a.recent.package.form.factor.with.particular.issues.
when. it. comes. to. surface. mounting. is. package-on-package,. or. PoP.. As.
shown.again.in.Figure 3.6,.a.PoP.structure.is.very.unbalanced.and.top.
Solder balls
Epoxy overmold
PCB substrate
Chip
Bottom
view
Side View
Figure 3.5  Example.of.a.ball.grid.array.package.(not.to.scale).
Figure 3.6  Example.of.a.package-on-package.(not.to.scale).

Page 49
30
Semiconductor packaging: materials interaction and reliability
heavy,.making.the.package.even.more.prone.to.warpage.during.initial.
package.assembly.and.after.solder.reflow,.as.shown.in.Figure 3.7.
3.7 Current and future trends
Though.technology.in.general.tends.to.always.be.rapidly.changing.in.the.
modern.age,.semiconductor.packaging.tends.to.move.a.bit.more.slowly,.at.
a.more.incremental.pace..That.is.not.to.say.changes.will.not.occur,.but.it.
does.take.into.account.a.primary.need.for.reliability.out.in.the.field..The.
longer.a.semiconductor.and.its.package.will.be.required.to.be.in.service.or.
how.critical.the.application.is,.the.more.conservative.the.technology..Good.
examples.are.the.types.of.semiconductor.packages.used.in.airplanes.or.
automobiles.compared.to.those.in.a.mobile.handset.or.television.
Nonetheless,.the.industry.is.subject.to.external.demands.and.regula-
tions.that.are.pushing.for.more.rapid.changes.in.some.cases.
3.7.1 Lead-free and halogen-free packaging
The.move.to.lead.(Pb)-free.and.halogen-free,.or.green,.packaging.due.to.
environmental,. health,. and. safety. regulations—namely. the. European.
Union’s. Restriction. of. Hazardous. Substances. or. RoHS—has. greatly.
affected. the. whole. surface-mount. process.. Acceptable. solder. alloys. not.
containing.lead.typically.require.peak.reflow.temperatures.in.the.range.
of. 30ºC. to. 40ºC. higher. than. was. needed. with. eutectic. lead-tin. solder..
This.elevated.temperature.exposure.often.means.the.old.bill.of.materials,.
which.worked.well.with.eutectic.tin-lead.solder,.will.wither.under.ther-
mal.stresses.and.will.be.unable.perform.reliably,.either.resulting.in.infant.
mortality.or.field.failures.
Slightly.different.issues.are.present.when.eliminating.halogens.from.
the.bill.of.materials,.but.nonetheless,.it.does.means.the.material.set.will.
need.to.be.changed,.and.it.will.need.to.be.compatible.with.the.aforemen-
tioned.requirements.for.lead-free..Therefore,.it.has.been.an.ongoing.pro-
cess. in. the. last. decade. or. more. to. update. the. bill. of. materials. creating.
semiconductor.packaging.to.meet.all.of.the.new.rules.and.regulations.
In.addition,.changes.extend.beyond.the.package,.to.the.circuit.board..
As. printed. circuit. boards. must. also. meet. the. new. criteria,. they. have.
undergone.changes.of.their.own,.from.new,.nonoxidizing.finishes.on.the.
Figure 3.7  Warped.package-on-package.(not.to.scale).

Page 50
Chapter three: Surface-mount technology
31
land.pads.instead.of.eutectic.lead-tin.solder.plating.to.changes.in.the.com-
position.and.appearance.of.the.solder.mask.to.the.type.and.composition.
of. the. laminate. material.. As. one. example,. green. has. been. a. popular.
color.for.solder.masks,.but.it.turns.out.that.to.achieve.that.color,.the.use.
of.materials.with.unacceptable.levels.of.halogens,.especially.chlorine,.is.
often.required..Another.is.the.various.options.of.finishes.and.coatings.to.
prevent.oxidation.of.lands,.whether.an.organic.solderability.preservative.
(OSP).or.using.the.combination.of.electroless.nickel.plating.followed.by.
immersion.gold.coating,.abbreviated.as.ENIG.
So,.compatibilities.must.be.found.throughout.the.different.levels.of.
electronics.assembly,.from.the.semiconductor.package.to.the.boards.to.the.
enclosure.to.meet.these.recent.environmental.regulations.
Bibliography
A.S..Chen,.W.J..Schaefer,.R.H.Y..Lo,.and.P..Weiler,.“A.Study.of.the.Interactions.of.
Molding. Compound. and. Die. Attach. Adhesive,. with. Regards. to. Package.
Cracking,”.presented.at.44th.ECTC,.Washington,.DC,.115–120,.May.1–4,.1994.
C.A.. Harper,. Electronic Packaging and Interconnection Handbook,. McGraw-Hill.
Professional,.New.York,.Chapter.6,.1991.
Intel. Corporation,. Intel® Manufacturing Enabling Guide,. Chapter. 1:. Component.
Surface.Mount.Technology.(SMT),.May.2010.
Intel. Corporation,. 2000 Packaging Databook,. Chapter. 7:. Leaded. Surface. Mount.
Technology.(SMT),.2000.
L.T..Nguyen,.R.H.Y..Lo,.A.S..Chen,.and.J.G..Belani,.“Molding.Compound.Trends.in.
a.Denser.Packaging.World.II:.Qualification.Tests.and.Reliability.Concerns,”.
IEEE Transactions on Reliability,.vol..42,.no..4,.518–535,.December.1993.
R.D..Skinner,.Ed.,.Basic Integrated Circuit Technology Reference Manual,.Integrated.
Circuit.Engineering.Corporation,.Section.3:.Packaging,.1993.
V..Solberg,.“Designers.Guide.to.Lead-Free.SMT,”.IPC APEX EXPO,.Las.Vegas,.NV,.
March.29–April.2,.2009.
B.. Wettermann,. “PoP. Rework:. Process. Control. and. Using. the. Right. Materials.
Increases.Yield,”.Advanced Packaging,.September.13,.2010.
What Is SMT Surface Mount Technology,. www.radio-electronics.com/info/data/
smt/what-is-surface-mount-technology-tutorial.php

Page 51

Page 52
33
chapter four
Other packaging needs
4.1 Objectives
•. List.and.categorize.other.devices.and.technologies.that.require.some.
form.of.electronic.packaging.
•. Discuss. current. status. and. future. developments. for. these. other.
devices.and.technologies.
4.2 Introduction
This.chapter.looks.at.electronic.packaging.needs.for.specialized.functions.
and.devices,.as.well.as.specialized.semiconductor.technologies.
4.3 Tape automated bonding
Tape.automated.bonding.(TAB).is.an.alternate.method.to.wire.bonding.for.
creating.interconnections.from.chip.to.lead.frame.or.substrate.
Introduced.into.production.during.the.mid-1970s,.TAB.saw.its.peak.
usage.in.the.1980s.to.early.1990s,.when.the.fine.pitch.capability.in.gold.
thermosonic. wire. bonding. was. still. lacking,. and. overall. throughput.
speeds.for.wire.bonding.were.still.relatively.slow..In.TAB,.the.chips.and.
their.respective.bond.pads.are.attached.simultaneously—which.is.dubbed.
gang bonding—to.a.continuous.tape.carrier,.which.becomes.a.temporary.
support.for.all.subsequent.manufacturing.steps..Prior.to.gang.bonding,.
either. the. bond. pads. or. the. lead. tips. receive. metallic. bumps,. typically.
plated.gold.
Table 4.1.describes.the.TAB.process.steps..After.the.wafer.is.sawed.up.
into.individual.chips,.each.chip.is.bonded.to.a.reel.of.flexible,.polyimide-
based.tape,.with.the.metal.leads.cantilevered.over.the.central.hole.in.the.
tape.. The. leads. are. all. bonded. together. into. the. inner. leads.. Figure  4.1.
shows.how.the.inner.TAB.leads.are.now.connected.to.the.chip..Next,.the.
chip.is.connected.to.a.lead.frame.or.substrate.via.gang.bonding.the.other.
end,.or.outer.lead.bonding.

Page 53
34
Semiconductor packaging: materials interaction and reliability
4.4 Micro electro-mechanical systems (MEMS)
MEMS. (Micro. Electro-Mechanical. Systems). devices. are. packaged. in. a.
large.variety.of.ways.due.to.the.great.variation.in.requirements..These.
requirements,. and. the. resulting. package. solutions,. go. beyond. those.
imposed.on.semiconductor.packaging.and.result.in.an.unusual.variety.
of.packages..For.example,.MEMS.are.used.for.vacuum.and.atmospheric.
control,. as. optical. devices,. as. electrostatic. discharge. (ESD). devices,. for.
fluid.analyzers,.and.the.list.goes.on..Note.that.many.devices.considered.
as.MEMS.actually.have.no.moving.mechanical.parts.
The.first.choice.to.package.a.MEMS.device.is.a.standard,.off-the-shelf.
semiconductor. package.. For. example,. from. STMicroelectronics,. a. stan-
dard. 16-lead. quad. flat. no-lead. package. is. used. for. a. three-axis. digital.
output. MEMS. accelerometer. and. motion. sensor. that. is. known. to. have.
been.used.in.the.iPhone.3G.iteration..Indeed,.all.of.STMicroelectronics’.
accelerometers.and.gyroscopes.are.packaged.in.quad.flat.no-lead.(QFN).
types,.ranging.in.sizes.as.small.as.3.0.by.3.0.by.0.9.mm.to.as.large.as.4.4.
by.7.5.by.1.0.mm.
The.motion.sensors.generally.avoid.issues.with.overmolding.“gum-
ming.up”.the.mechanical.parts.by.capping.that.area.to.make.a.protective.
cavity..With.a.cap,.a.MEMS.chip.simply.looks.like.a.stacked-die.configura-
tion..Other.MEMS.device.types.may.require.more.adaptations.or.devia-
tions.from.standard.semiconductor.(plastic).packaging.processes..MEMS.
for. optical. applications. or. with. mirror. arrays. (digital. light. processors.
Chip
Inner TAB leads
Figure 4.1  Inner.lead.tape.automated.bonding.(TAB).(not.to.scale).
Table 4.1  Tape.Automated.Bonding.(TAB).Processing.
Steps
Key
Steps
TAB Process
A
Singulate.wafer.into.individual.chips
B
Reel.of.flexible.tape
C
Chip.mounted.on.tape.side—inner.lead.bonding
D
Electrical.test.on.tape
E
Chip.bonding.to.lead.frame—outer.lead.bonding
F
Chip.bonding.to.substrate—outer.lead.bonding
Source: .A dapted.from Karel.Kurzweil,.Electrocomponent Science and
Technology,.6,.159–163,.1980.

Page 54
Chapter four: Other packaging needs
35
[DLPs]).often.require.a.cavity.package.and.an.opening.on.top.to.expose.
the.MEMS.section.to.the.visible.world..Something.similar.is.likely.needed.
for.MEMS.microphones,.which.must.ensure.that.sounds.reach.the.MEMS.
device.clearly.and.unimpeded..A.key.emerging.technology.used.to.reduce.
cost. and. improve. performance. of. MEMS. devices. is. the. integration. of.
MEMS.devices.with.standard.semiconductor.chips,.which.provide.drive,.
control,.and.signal.processing.functions..This.approach.enables.increased.
integration.and.reduction.in.cost.
MEMS.devices.are.sometimes.designed.to.use.wafer-level.packaging.
(WLP)..Again.as.an.example,.an.all-digital.MEMS.microphone.on.a.sin-
gle.complementary.metal.oxide.semiconductor.(CMOS).chip.by.Akustica.
(acquired.by.Bosch.in.the.summer.of.2009).is.in.a.four-lead.WLP..Some.
wafer-level.methods.use.overmolding;.some.use.wafer-to-wafer.bonding;.
and. some. build. a. cavity. within. the. MEMS. structure. and. seal. it. at. the.
device.fabrication.level,.often.with.another.piece.of.silicon.
However,. in. many. cases,. standard. package. offerings. often. end. up.
being.inadequate.for.specific.MEMS.applications,.so.engineers.must.mod-
ify.the.design.or.design.a.unique.package.for.manufacturing..The.selec-
tion.and.design.of.a.MEMS.package.can.be.a.major.portion.of.the.effort.
needed.to.bring.a.MEMS.product.to.market.
Table 4.2.shows.some.of.the.packaging.methods.used.for.MEMS,.and.
Table 4.3.presents.MEMS.packaging.examples.
4.5 Image sensor modules
An.image.sensor.package.is.an.optical.element,.whether.based.on.a.com-
plementary.metal.oxide.semiconductor.(CMOS).or.charge.coupled.device.
(CCD).packaged.with.an.optical.lens.that.enables.the.imaging.functions.
Packaging. needs. for. digital. image. sensors. have. their. own. special.
requirements..For.one.thing,.the.sensors.need.to.“see,”.so.nothing.opaque.
can.cover.the.chip.surface..Also,.the.sensor.surface.and.the.clear.cover.
must. be. kept. extremely. clean. and. handled. carefully,. so. that. dust. and.
scratches.do.not.degrade.the.image.capture.quality..Image.sensor.pack-
ages.may.come.in.many.different.formats,.all.derived.from.established.
package.types..One.of.the.more.commonly.used.ones.is.the.LCC.(leadless.
chip.carrier);.an.example.using.a.plastic.molded.body.with.an.opening.on.
the.top.surface.for.the.image.sensor.is.shown.in.Figure 4.2..Images.sensors.
packaged.inside.a.LCC.are.cavity-up,.wire.bonded,.and.given.a.glass.lid..
They.offer.a.small.form.factor.and.excellent.thermal.performance.
4.6 Memory cards
The. advent. of. the. digital. still. camera. brought. about. the. initial. growth.
and. demand. for. compact,. removable. memory. cards.. Unfortunately,. at.

Page 55
36
Semiconductor packaging: materials interaction and reliability
least. for. the. consumer,. product. development. left. to. free. market. forces.
usually.means.a.proliferation.of.many.incompatible.formats..And.so.was.
the.case.with.memory.cards—at.recent.count,.there.are.approximately.14.
types,.including.variations.on.a.given.basic.form.factor..Figure 4.3.shows.
a.secure.digital.(SD).card,.which.is.only.one.of.the.many.different.kinds.
of.memory.card.formats.currently.available.on.the.market..Table 4.4.lists.
most.of.the.available.formats.and.their.specifications.
Table 4.2  Package.Types.Used.for.Micro.Electro-Mechanical.System.(MEMS).
Devices
Type of Package
Applications
Characteristics
Plastic.overmolded,.
leaded.and.leadless
Resonators,.
accelerators,.inertial.
sensors
Low.cost
Premolded.plastic.air.
cavity,.leaded.and.
leadless
Pressure.sensors,.
accelerators,.
microphones
Low-cost.cavity.
package
Ceramic.with.metal.lid.
or.metal.cap
Lab-on-a-chip,.optical.
devices,.radio-
frequency.(RF).switches
Highly.stable,.costly,.
complex.to.engineer.
and.fabricate;.control.of.
cavity.environment;.
dry,.vacuum,.inert.gas,.
and.so.forth
Ceramic.with.glass.cover
Optical.applications,.
charge-coupled.device.
(CCD).packages,.digital.
light.processor.(DLP)
Stable,.moderate.cost,.
optical.window
TO-5.with.hole.or.
window
Pressure.sensors,.some.
optical.devices
Low.cost,.widely.
available
Glass-on-glass
Optical.applications,.
displays
Large.cavity.packages,.
sometimes.with.
stand-offs
MEMS.on.organic.
substrates.with.glass.
cover
Optical.switches,.
displays
Quick.to.market,.low.
cost
MEMS.on.substrate—
organic,.ceramic,.and.so.
forth—wire.bond,.
partial,.or.total.
encapsulation
Ink-jet.print.heads,.
fingerprint.readers
Wafer.level.(structure.
built,.then.singulate)
Camera.modules
Lowest.cost.in.volume.
production
Source: .A dapted. from International Technology Roadmap for Semiconductors, 2007 Edition,.
Assembly.and.Packaging.chapter.

Page 56
Chapter four: Other packaging needs
37
T
a
b
le 4
.3 
M
icro
.E
le
ctro
-M
e
ch
a
n
ica
l.S
y
stem
s.(M
E
M
S
).P
a
ck
a
g
in
g
.E
x
a
m
p
le
s
Mark
et
A
utomotiv
e
Consumer
Tw
o-
Dimensional
(2D) Optical
Switch
T
hree-Dimensional
(3D) Optical Switch
Netw
ork Switch
W
ireless
Application
Acceleration,.
airbag
.sensor
V
ideo
.games,.
appliances
Optical.
add-drop
.
multiplexer.
(OADM)
W
ide-area
.network
.
(W
AN).and
.local.area
.
network
.(LAN)
Electronic.
switches
Surface
.acoustic.
wave
.(SA
W).
filters
MEMS
.type
T
wo-axis.
accelerometer
Three-axis.
accelerometer
64
.mirrors,.90°.
motion
180°.full.motion
.
mirrors
Contact.switch
Planar.filter
Package
.size
T
O-8,.14L
.
CerDIP
Surface-mount.
ceramic.leaded
.
chip
.carrier.
(CLCC)
Custom
.metal,.
82
.mm
2
Custom
.ceramic,.184
.
mm
2
Low-temperature
.
co-fired
.ceramic.
(L
TCC),.27
.mm
2
Printed
.wiring
.
board
.(PWB),.40
.
mm
2
Clean
.room
100;.10,000
100;.10,000
100;.10,000
100;.10,000
100
10,000
Die
.bond
Epoxy
Epoxy
Au-Sn
.Eutectic
Epoxy
Au-Sn
.Eutectic
Epoxy
W
ire
.bond
0.7–1.0
.Au
.ball
0.7–1.0
.Au
.ball
1.25
.Al,.1.25
.Au
1.25
.Au
.wedge/ball
1.0–1.25
.Au
.ball
1.0
.Au
.ball
Seal
Seam
.seal
Molded
Seam
.seal
Seam
.seal
Epoxy
Epoxy
.lid
.seal
Leak
.test
Gross/fine
None
Gross/fine
Gross/fine
Gross/fine
None
Additional
N/A
N/A
Fiber.optics,.
connectors
Flex
.circuit,.
connectors
PWB
.connectors
SMT
.connectors
Manufacturing
.
level
Production
Production
Preproduction
Preproduction,.
research
.and
.
development.(R&D)
Preproduction,.
prototype
Preproduction,.
prototype
Source:
Adapted
.from
International Technology Roadmap for Semiconductors, 2007 Edition
,.Assembly
.and
.Packaging
.chapter.

Page 57
38
Semiconductor packaging: materials interaction and reliability
Figure 4.2  Image.sensor.package..(From.Wikimedia.Commons.)
Figure 4.3  Secure.digital.(SD).memory.card..(From.WP.Clipart.)

Page 58
Chapter four: Other packaging needs
39
T
a
b
le 4
.4 
M
em
o
ry
.C
a
rd
.F
o
rm
ats
Card F
ormat
Size (mm)
T
otal
Interface
Pin
Count
Data
Interface Pin Count
Interface
Clock Rate (MHz)
Maximum Data Rate
at Host
Interface (Mb
ytes/
sec)
V
oltage
(V)
Built-In Memory
Controller
Security
PCMCIA
85.6.×
.53.8.×
.3.3.(T
ype.I);.
85.6.×
.53.8.×
.5.(T
ype.II);.85.6.
×
.53.8.×
.10.4.(T
ype.III)
68
8,.16,.or.32
16.(PC
.
Card);.132. (CardBus)
3.3,.5
Y
es
No
Compact.Flash
42.8.×
.36.4.×
.3.3.(T
ype.I);.
42.8.×
.36.4.×
.5.(T
ype.II)
50
8.or.16
8
16
3.3,.5
Y
es
No
Smart.Media
37.×
.45.×
.0.8
22
8
N/A
20
3.3,.5
Y
es
No
Multimedia.card
.
(MMC)
24.×
.32.×
.1.4
7
1
20
2.5
1.8,.3.3
Y
es
Optional
RS-MMC
24.×
.18.×
.1.4
7
1
20
2.5
1.8,.3.3
Y
es
Optional
MMC
.plus
24.×
.32.×
.1.4
13
8
52
52
1.8,.3.3
Y
es
Optional
MMC
.mobile
24.×
.18.×
.1.4
13
8
52
52
1.8,.3.3
Y
es
Optional
Secure.Digital.(SD)
24.×
.32.×
.2.1
9
4
20
10
3.3
Y
es
Y
es
Mini.SD
20.×
.21.5.×
.1.4
9
4
20
10
3.3
Y
es
Y
es
Micro
.SD
10.×
.15.×
.1.1
9
4
20
10
3.3
Y
es
Y
es
Memory
.Stick
21.×
.50.×
.2.8
10
1
24
3
3.3
Y
es
No
Memory
.Stick
.Duo
20.×
.31.×
.1.6
10
1
24
3
3.3
Y
es
No
Memory
.Stick
.Pro
20.×
.50.×
.2.8
10
4
40
20
1.8,3.3
Y
es
Y
es
Memory
.Stick
.Pro
.
Duo
20.×
.31.×
.1.6
10
4
40
20
1.8,.3.3
Y
es
Y
es
xD-Picture.Card
25.×
.20.×
.1.7
18
8
N/A
20
3.3
Y
es
No
USB
.Flash
.Drive
V
arious
4
1.
(differential)
12.(full.
speed);.480.
(high
.
speed)
1.5.(full.
speed);.60.
(high
.speed)
5
Y
es
Optional
Source:
Adapted
.from
.Brian
.Dipert,.
EDN
,.53–61,.July
.8,.2004.
Note:
PCMCIA,.Personal.Computer.Memory
.Card
.International.Association
.cards;.RS,.reduced
.size.

Page 59
40
Semiconductor packaging: materials interaction and reliability
After.digital.still.cameras,.the.next.market.memory.card.conquered.
was.mobile.phones..As.handsets.morphed.into.camera-phones.and.smart-
phones,.the.need.for.extra.memory.capacity.became.readily.apparent,.and.
soon.mobile.phones.with.slots.for.removable.memory.cards.were.ubiq-
uitous..Most.handsets.use.a.smaller.version.of.the.SD.card.format,.either.
mini-SD.or.the.even.smaller.micro-SD.
Memory. Stick. is. a. format. developed. by. Sony,. and. generally. their.
products.are.the.only.ones.using.that.form.factor..The.xD-Picture.card.is.
typically.found.only.in.digital.cameras.
Even.TVs.and.printers.now.often.sport.memory.card.slots.in.the.front,.
for.directly.downloading.data.and.images.
The.number.of.formats.seems.to.be.stabilizing.now,.and.many.of.the.
formats.are.falling.into.disuse.or.have.become.obsolete.for.various.rea-
sons.(size,.memory.capacity.limitations,.etc.)..Among.those.no.longer.or.
rarely. used. include. Memory. Stick,. xD-Picture. Card,. and. Smart. Media..
Currently,. the. two. card. formats. commonly. found. in. retail. outlets. are.
SD. and. its. various. micro. and. mini. variations,. and. CompactFlash. (CF)..
SD.is.the.more.dominant,.supported.in.a.wide.range.of.products.from.
digital.cameras.to.laptops.to.smartphones.to.televisions..CF.is.generally.
only.found.in.high-end.SLR.(single-lens.reflex).digital.cameras.and.other.
specialty.applications..These.two.card.formats.are.likely.to.remain.in.the.
marketplace.for.some.time,.as.both.have.upcoming.transfer.speed.and.
memory.capacity.improvements.in.the.works.by.their.respective.standard.
bodies.
4.7 Packaging needs for solar technology
Traditional. semiconductor. package. technologies. are. not. employed. in.
packaging. solar. cells. and. solar. cell. arrays.. However,. there. are. unique.
packaging.requirements.to.package.solar.cells.and.solar.cell.arrays.against.
the.elements.
Solar.cell.modules.face.temperature.extremes.and.must.have.a.very.
long.life.compared.to.almost.any.other.semiconductor.packaging.require-
ment..The.current.state.of.the.art.for.the.photovoltaic.modules.used.in.
solar.cell.arrays.is.as.follows:
•. Semiconductor.thickness.180.μみゅーm
•. Soldered.with.high-throughput.tabber-stringer
•. Vacuum.lamination
•. EVA.(ethylene-vinyl.acetate).as.encapsulant
•. Guaranteed.lifetime.of.25.years

Page 60
Chapter four: Other packaging needs
41
The.continued.expansion.of.solar.power.and.the.changes.anticipated.in.solar.
cell. technology. and. operational. demands. will. eventually. move. to. more.
stringent.requirements..These.new.requirements.will.include.the.following:
•. Low-stress. interconnection. for. very. thin. solar. cells. (between. 100-.
and.150-μみゅーm.thick)
•. High-throughput.lamination.technology
•. Lead-free.soldering.solutions
•. 30-years.lifetime
•. Design.for.easy.recycling.at.end.of.life
Semiconductor.packaging.only.comes.directly.into.play.with.solar.collec-
tion.systems..Semiconductors.are.required.to.regulate.voltages.and.cur-
rent,.as.well.as.DC-to-AC.power.inverters.and.other.power.management.
purposes.. These. power. management. chips. come. in. standard. package.
form.factors.and.do.not.have.extraordinary.requirements.specific.to.solar.
power.configurations.
Bibliography
Akustica,.Inc.,.www.akustica.com
“CMOS.Image.Sensor.Packaging:.Picture.the.Challenges,”.Prismark Partners LLC,.
November.1999.
C..Crossman,.“Device.Reads,.Writes.in.12.Formats,”.The Seattle Times,.March.21,.
2005.
B..Dipert,.“Pick.a.Card,”.EDN,.53–61,.July.8,.2004.
B..Dipert,.“Flash.Forward.to.the.Future,”.EDN,.November.1,.2004.
Y.. Emoto,. N.. Ohikata,. Y.. Kawakami,. M.. Konda,. T.. Yamamoto,. K.. Chiba,. and.
N. Kunii,.“Development.of.Molded.TAB.Package.Technology,”.Nippon Steel
Technical Report,.no..56,.1–6,.January.1993.
B..Howard,.“Flash.Memory:.Pick.a.Card,”.PC Magazine,.September.2,.2003.
International Technology Roadmap for Semiconductors, 2007 Edition,. Assembly. and.
Packaging.chapter.
R.C..Johnson,.“MEMS.Mics.Moving.into.Mainstream,”.EE Times,.September.22,.
2008.
R.C..Johnson,.“Bosch.Acquires.MEMS.Microphone.Pioneer.Akustica,”.EE Times,.
August.19,.2009.
K.. Kurzweil,. “An. Installed. Tape. Automated. Bonding. Unit,”. Electrocomponent
Science and Technology,.vol..6,.159–163,.1980.
K.. Kurzweil,. “Tape. Automated. Bonding. for. High. Density. Packaging,”.
Electrocomponent Science and Technology,.vol..8,.15–19,.1981.
R.H.Y..Lo.and.E..Tjhia,.“Backsputtering.Etch.Studies.in.Wafer.Bumping.Process,”.
Solid State Technology,.pp..91–94,.June.1990.
R.. Lo,. “Upcoming. Trends. in. IC. Package. Technology,”. SEMICON Taiwan 2001,.
September.17–19,.2001.

Page 61
42
Semiconductor packaging: materials interaction and reliability
R..Lo.and.H.P..Takiar,.U.S..Patent.No..5,617,297:.Encapsulation.filler.technology.for.
molding.active.electronics.components.such.as.IC.cards.or.PCMCIA.cards,.
April.1,.1997.
SanDisk.presentation,.Lehman Brothers T4 2004—Technology and Telecom Trends for
Tomorrow,.December.8,.2004.
S..Shankland,.“CompactFlash.Allies.Rally.Against.Dominant.SD,”.CNET News,.
December.14,.2010.
Siliconware.Precision.Industries.Ltd.,.www.spil.com.tw/
STMicroelectronics,.Data.Sheet,.LIS221DL,.April.2008.
STMicroelectronics,.Product.Brochure,.MEMS Motion Sensors,.October.2009.
“STMicroelectronics. Rolls. Out. Nano. Three-Axis. Linear. Accelerometers,”. EDA
Geek,.October.2,.2007.

Page 62
section two
Package reliability

Page 63

Page 64
45
chapter five
Reliability testing
5.1 Introduction
Once. the. chip. has. been. packaged. and. electrically. tested,. there. is. the.
requirement.that.the.package.demonstrate.field.reliability..Because.it.is.
impossible.to.assess.that.in.real.time.and.on.all.device/package.combina-
tions.out.in.the.field,.accelerated.testing.is.done.on.a.statistically.signifi-
cant.sample.size.to.confirm.operational.reliability.
Qualification. or. reliability—accelerated—tests. are. aimed. at. the.
following:
•. Inducing.typical.failure.modes.rapidly
•. Decreasing.the.amount.of.time.required.to.assess.the.reliability.of.a.
given.package.and.device.combination
•. Screening.out.defects.early.and.quickly
•. Forecasting.what.might.be.the.useful.lifetime.of.a.given.part.based.
on.acceleration.factors.(This.useful.life.period.can.be.called.mean.
time.to.failure.[MTTF].in.the.case.of.nonrepairable.semiconductor.
devices.in.packages.)
This.is.illustrated.in.Figure 5.1,.which.is.called.the.reliability.bathtub.curve.
Naturally,. these. tests. are. only. useful. if. the. failure. mechanisms.
induced. reflect. those. encountered. under. normal. operating. conditions..
Even.though.semiconductor.packages.are.generally.robust.and.do.their.
job.of.protecting.the.chip,.or.chips,.within,.they.are.nevertheless.subject.
to.a.variety.of.failure.modes.
Each.material.component.of.a.package.exhibits.a.typical.or.common.
failure.mode.peculiar.to.that.material.or.purpose,.though.the.final.mani-
festation.may.be.common.across.several.materials..For.instance,.underfill.
materials.can.crack.during.temperature.or.power.cycling,.either.during.
reliability.testing.or.during.actual.field.operation..The.thermal.expansion.
mismatch. between. the. chip. and. underfill. causes. stress. concentrations.
in.certain.locations,.like.at.a.die.corner..As.the.crack.propagates.during.
continued. stressing,. the. crack. opens. up. the. chip–underfill. interface. or.
another.weakened.section,.causing.either.interconnect.fatigue.or.an.elec-
trical.failure.in.the.chip’s.dielectric.

Page 65
46
Semiconductor packaging: materials interaction and reliability
5.2 Background
Standards.created.by.industry.organizations.help.determine.the.number.
and.type.of.tests,.as.well.as.test.conditions,.that.best.cover.the.possible.fail-
ure.mechanisms.in.a.consistent.manner.across.all.suppliers.in.the.industry..
The.original.standard.developed.and.used.by.the.semiconductor.industry.
was. Mil-Std-883,. which. was. used. to. qualify. semiconductor. devices. and.
packages.for.military.and.aerospace.applications,.but.in.those.early.days,.
most,. if. not. all,. of. the. packaging. done. was. hermetic,. with. chips. sealed.
inside.metal.cans.or.sandwiched.between.ceramic.substrates.and.caps.
Later,. the. industry. association. JEDEC. (Joint. Electron. Devices.
Engineering.Council,.now.officially.known.as.JEDEC Solid State Technology
Association)—mentioned.in.Chapter.2.as.the.standards.body.for.the.semi-
conductor.industry—created.testing.standards.applicable.for.plastic.semi-
conductor.packages..The.most.current.set.of.reliability.and.qualification.
criteria.fall.under.the.JESD22.family.of.test.methods.
5.3 Examples of reliability tests
There.are.many.different.reliability.tests,.each.aimed.at.eliciting.a.certain.
failure.mode..There.is.also.some.overlap.between.various.tests,.as.some.
are.considered.too.harsh.to.mimic.more.benign.operating.conditions.(i.e.,.
a. desktop. PC. in. an. office. environment. versus. a. ruggedized. laptop. for.
military. operations. or. an. embedded. computer. module. under. the. hood.
of.an.automobile)..The.same.goes.for.the.test.conditions.used..Also,.the.
semiconductor.suppliers.can.pick.and.choose.the.types.and.specifications.
of.the.tests.and.vary.them.away.from.industry.standards,.as.per.the.needs.
and.requirements.of.their.end.customers..Some.of.the.important.tests.are.
listed.in.Table 5.1.
Customer Use Hours
Infant
mortality
Useful life
Wear out
(Fails
found via
screening)
(Beyond
normal
product
life)
Failure Rate
Figure 5.1  Reliability.bathtub.curve.for.a.device’s.useful.life.(not.to.scale).

Page 66
Chapter five: Reliability testing
47
Table 5.1  Partial.List.of.Reliability.Tests
Test
Abbreviation
Goal
Test Conditions
Preconditioning
Precon
Mimics.solder.
reflow.board.
attachment.for.
surface.mount.
plastic.packages;.
done.prior.to.other.
reliability.tests
See.Table 5.2
High-temperature.
storage
HTS
Induce.bond.pad.
metallization.
failures.through.
heat.and.halides
1000.hours.at.150ºC.
or.175ºC
Temperature.
cycling
TC
Thermal.stressing.
of.the.physical.
construction.of.the.
chip.and.package
–65ºC.to.150ºC.for.
1000.cycles.in.air
Thermal.shock
TS
Thermal.stressing.
of.the.physical.
construction.of.the.
chip.and.package
–65ºC.to.150ºC.for.
100.to.1000.cycles.
in.liquid
Temperature-
humidity-bias
THB
Passivation.
integrity.against.
ionics.under.
moisture.and.
electrical.bias.
conditions
1000.hours.at.
85ºC/85%.RH.
(relative.humidity)
Autoclave
ACLV
Passivation.
integrity.against.
ionics.under.
moisture.
conditions
168.hours.or.more.
at.121ºC.and.
between.15.and.30.
psig
Highly.accelerated.
temperature.and.
humidity.stress.
testing
HAST
An.accelerated.
version.of.the.THB.
test
110ºC.or.130ºC.
under.85%.RH.and.
under.vapor.
pressure.for.at.least.
96.or.more.hours
Source: .A dapted. from. JEDEC,. JEP150, Stress-Test-Driven Qualification of and Failure
Mechanisms Associated with Assembled Solid State Surface-Mount Components,. May.
2005,.table 1.

Page 67
48
Semiconductor packaging: materials interaction and reliability
There.are.JEDEC.standards.(for.instance,.JESD74).to.help.determine.
a.statistically.significant.sample.size,.which.should.be.drawn.from,.and.
divided.into,.a.minimum.of.three.nonconsecutive.production.lots,.to.help.
determine.early.life.failure.rates.(ELFRs).
5.3.1 Preconditioning conditions
The.requirements.can.vary.considerably,.depending.on.a.given.package.
form. factor’s. sensitivity. to. moisture. or. moisture. sensitivity. level. (MSL).
level,.which.is.detailed.in.the.IPC/JEDEC.J-STD-020.document..The.table.
detailing.MSL.levels.in.shown.in.Table 5.2..The.current.industry.criteria.
are.laid.out.in.Table 5.3,.which.shows.the.typical.sequence.of.events..The.
solder.reflow.profiles.specified.for.a.given.package.form.factor.are.given.
in.Table 5.4.and.illustrated.in.Figure 5.2.
As.stated.in.the.title.of.JESD22-A113F,.the.preconditioning.test.is.done.
prior.and.in.addition.to.other.reliability.tests..In.other.words,.parts.set.aside.
to.under.temperature.cycling.would.undergo.a.preconditioning.sequence.
before.starting.the.temperature.cycling.test.sequence..Preconditioning.is.
not.intended.as.a.stand-alone.reliability.or.qualification.test.
Preconditioning.is.intended.to.simulate.the.viability.of.the.packages.
during. board. assembly. and. mimic. the. environment. of. the. production.
floor,.where.packages.might.sit.out.in.the.open,.away.from.their.dry-pack.
bags.or.from.a.dry.box,.and.be.saturated.with.moisture.
As.already.discussed.in.the.chapters.for.molding.compounds.and.for.
interfacial.interaction,.the.goal.of.preconditioning.is.to.see.whether.the.
package-die.system.can.resist.the.phenomenon.of.solder.reflow.package.
cracking,.otherwise.named.popcorning.
5.3.1.1 Package failure mode: package crack or popcorning
Indirect.failures.from.moisture.include.package.popcorn.cracking.of.large.
surface-mount.packages.during.solder.reflow..As.an.aside,.the.term.pop-
corn cracking.refers.to.the.often-audible.fracture.of.the.interface.between.
molding.compound.and.chip.or.its.lead.frame.or.substrate,.commonly.due.
to.insufficient.interfacial.adhesion,.especially.if.sufficient.moisture.is.pres-
ent..Figure 5.3.shows.the.various.interfaces.where.delamination.can.occur.
and.stress.concentration.areas.develop.for.cracks.to.propagate..Figure 5.4.
illustrates.the.sequence.of.events.leading.to.package.failure..Even.without.
the.appearance.of.an.external.crack,.the.package’s.integrity.is.almost.cer-
tainly.degraded.from.delamination.between.internal.interfaces.
5.3.2 Temperature cycling and thermal shock
The.purpose.of.temperature.cycling.is.to.check.on.package.integrity.in.
spite. of. the. coefficient. of. thermal. expansion. mismatches. between. the.

Page 68
Chapter five: Reliability testing
49
T
a
b
le 5
.2 
P
re
co
n
d
itio
n
in
g
.T
e
st.C
o
n
d
itio
n
s
Accelerated Equiv
alent
a
L
ev
e
l
Floor Life
T
im
e
Soak
Requirements
C
o
n
d
itio
n
Standard
T
im
e
(h
o
u
rs)
C
o
n
d
itio
n
eV 0.40–0.48
T
im
e
(h
o
u
rs)
eV 0.30–0.39
T
im
e
(h
o
u
rs)
C
o
n
d
itio
n
1
Unlimited
≤30ºC/85%
.RH
168
.+5/–0
85ºC/85%
.RH
N/A
N/A
N/A
2
1
.year
≤30ºC/60%
.RH
168
.+5/0
85ºC/60%
.RH
N/A
N/A
N/A
2a
4
.weeks
≤30ºC/60%
.RH
696
b .+5/0
30ºC/60%
.RH
120
.+1/0
168
.+1/–1
60ºC/60%
.RH
3
168
.hours
≤30ºC/60%
.RH
192
b .+5/0
30ºC/60%
.RH
40
.+1/0
52
.+1/0
60ºC/60%
.RH
4
72
.hours
≤30ºC/60%
.RH
96
b .+5/0
30ºC/60%
.RH
20
.+1/0
24
.+1/0
60ºC/60%
.RH
5
48
.hours
≤30ºC/60%
.RH
72
b .+5/0
30ºC/60%
.RH
15
.+1/0
20
.+1/0
60ºC/60%
.RH
5a
24
.hours
≤30ºC/60%
.RH
48
b .+5/0
30ºC/60%
.RH
10
.+1/0
13
.+1/0
60ºC/60%
.RH
6
T
ime.on
.
label.(T
OL)
≤30ºC/60%
.RH
T
OL
30ºC/60%
.RH
N/A
N/A
N/A
Note:
Suppliers.may
.extend
.the.soak
.times.at.their.own
.risk.
Source:
.A dapted
.from
.JEDEC,.
IPC/JEDEC
J-STD-020D.1, Moisture/Reflow
Sensitivity Classification
for Nonhermetic Solid State Surface Mount Devices
,.
March
.2008,.table 5-1.
a.
C
a
u
tio
n
:.T
o
.u
se.th
e.“
a
ccelera
ted
.eq
u
iv
a
len
t”
.so
a
k
.co
n
d
itio
n
s,.co
rrela
tio
n
.o
f.d
a
m
a
g
e.resp
o
n
se.(in
clu
d
in
g
.electrica
l,.a
fterso
a
k
,.a
n
d
.refl
o
w
).
sh
o
u
ld
.b
e.esta
b
lish
ed
.w
ith
.th
e.“
sta
n
d
a
rd
.so
a
k
.co
n
d
itio
n
s..A
ltern
a
tely,.if.th
e.k
n
o
w
n
.a
ctiv
a
tio
n
.en
erg
y
.fo
r.m
o
istu
re.d
iffu
sio
n
.o
f.th
e.p
a
ck
-
a
g
e.m
a
teria
ls.is.in
.th
e.ra
n
g
e.o
f.0
.4
0
.to
.0
.4
8
.eV
.o
r.0
.3
0
.to
.0
.3
9
.eV
,.th
e.“
a
ccelera
ted
.eq
u
iv
a
len
t”
.m
a
y
.b
e.u
sed
..A
ccelera
ted
.so
a
k
.tim
es.m
a
y
.
v
a
ry
.d
u
e.to
.m
a
teria
l.p
ro
p
erties.(e.g
.,.m
o
ld
.co
m
p
o
u
n
d
,.en
ca
p
su
la
n
t,.etc.)..JE
D
E
C
.d
o
cu
m
en
t.JE
S
D
2
2
2
-A
1
2
0
.p
ro
v
id
es.a
.m
eth
o
d
.fo
r.d
eter-
m
in
in
g
.th
e.d
iffu
sio
n
.co
effi
cien
t.
b
.
The.standard
.soak
.time.includes.a.default.value.of.24.hours.for.semiconductor.manufacturer’s.exposure.time.(MET).between
.bake.and
.bag
.
and
.includes.the.maximum
.time.allowed
.out.of.the.bag
.at.the.distributor’s.facility..If.the.actual.MET
.is.less.than
.24.hours,.the.soak
.time.may
.
be.reduced..For.soak
.conditions.of.30ºC/60%
.RH,.the.soak
.time.is.reduced
.by
.1.hour.for.each
.hour.the.MET
.is.less.than
.24.hours..For.soak
.
conditions.of.60ºC/60%
.RH,.the.soak
.time.is.reduced
.by
.1.hour.for.each
.5.hours.the.MET
.is.less.than
.24.hours..If.the.actual.MET
.is.greater.than
.
24.hours,.the.soak
.time.must.be.increased..For.soak
.conditions.of.30ºC/60%
.RH,.the.soak
.time.is.increased
.1.hour.for.each
.hour.the.actual.MET
.
exceeds.24.hours..For.soak
.conditions.of.60ºC/60%
.RH,.the.soak
.time.is.increased
.1.hour.for.each
.5.hours.the.actual.MET
.exceeds.24.hours.

Page 69
50
Semiconductor packaging: materials interaction and reliability
various.materials.and.their.respective.interfaces.within.the.plastic.pack-
age.. Unlike. hermetic. packages,. the. die. surface. is. not. isolated. from. the.
other.material.surfaces.within.the.package..Good.contact.and.adhesion.
are.key.to.a.long.service.life..All.the.components—the.semiconductor.chip,.
the. metal. lead. frame. or. organic. substrate,. the. polymer-based. molding.
compound.or.die.attach.adhesive—within.a.package.will.likely.have.very.
different.expansion.and.contraction.rates.while.being.heated.or.otherwise.
Table 5.3  Steps.in.Conducting.Preconditioning.Testing
Step
Item
Details
1
Initial.electrical.test
Replace.any.failing.devices;.optional.for.
testing.by.supplier
2
Visual.inspection
Replace.any.failing.devices;.optional.for.
testing.by.supplier
3
Temperature.cycling
Five.cycles.at.–40ºC.to.60ºC;.optional.
shipping.simulation.based.on.product.
requirements
4
Bake
24.hours.at.125ºC;.optional.for.testing.by.
supplier
5
Moisture.soak
Soak.time.and.conditions.per.IPC/JEDEC.
J-STD-020.based.on.device.MSL.level
6
Reflow
Three.reflow.cycles.using.profiles.per.IPC/
JEDEC.J-STD-020,.document.rev.of.J-STD-020.
used;.SnPb.or.Pb-free.profile.based.on.device.
and.use.process
7
Flux.application
10.seconds.of.full.immersion.in.activated.
water-soluble.flux;.optional.for.testing.by.
user.or.second-level.configuration;.not.
required.for.ball.grid.array.(BGA),.column.
grid.array.(CGA),.and.land.grid.array.(LGA).
packages
8
Cleaning
Deionized.(DI).water.rinse;.remove.all.flux.
residual;.optional.for.testing.by.user.or.
second-level.configuration;.not.required.for.
BGA,.CGA,.and.LGA.packages
9
Drying
Room.ambient.drying;.optional.for.testing.
by.user.or.second-level.configuration;.not.
required.for.BGA,.CGA,.and.LGA.packages
10
Final.electrical.test
If.all.devices.pass,.then.ready.for.reliability.
testing;.if.valid.failures.are.found,.then.
devices.may.have.been.tested.to.the.wrong.
MSL.level.or.something.is.substandard.with.
the.devices;.optional.for.testing.by.supplier
Source: .A dapted. from. JEDEC,. JESD22-A113F, Preconditioning of Plastic Surface Mount
Devices Prior to Reliability Testing,.October.2008,.Annex.A.

Page 70
Chapter five: Reliability testing
51
Table 5.4  Solder.Reflow.Profiles
Condition
Sn-Pb Eutectic
Assembly
Pb-Free Assembly
Preheat/soak
Minimum.temperature
100ºC
150ºC
Maximum.temperature
150ºC
200ºC
Time.from.minimum.to.
maximum
60.to.120.seconds
60.to.120.seconds
Ramp-up.rate
3ºC.per.second.
maximum
3ºC.per.second.
maximum
Liquidous.temperature.(TL)
183ºC
217ºC
Time.held.above.TL
60.to.150.seconds
60.to.150.seconds
Peak.package.body.
temperature
Between.220ºC.
and.235ºC,.
depending.on.size.
and.volume
Between.245ºC.and.
260ºC,.depending.on.
size.and.volume
Hold.time.within.5ºC.of.
peak.temperature
20.seconds
30.seconds
Ramp-down.rate
6ºC.per.second.
maximum
6ºC.per.second.
maximum
Time.from.25ºC.to.peak.
temperature
6.minutes.
maximum
8.minutes.maximum
Source: .A dapted.from.JEDEC,.IPC/JEDEC J-STD-020D.1, Moisture/Reflow Sensitivity
Classification for Nonhermetic Solid State Surface Mount Devices,.March.2008,.
table 5-2.
Time
Temperature
Preheat/Soak
Peak
Ramp up
Ramp down
Figure 5.2  Solder.reflow.profile.over.time.and.temperature.(not.to.scale).

Page 71
52
Semiconductor packaging: materials interaction and reliability
thermally.stressed,.as.already.illustrated.in.Table 1.3.and.shown.again.in.
Table 5.5..Cycling.between.expansion.and.contraction.causes.movement.
between.the.plastic,.epoxies,.metal.lead.frame,.and.chip..Because.the.chip.
expands.much.less.than.either.plastic.or.metal,.its.surface—along.with.
all.of.the.delicate.active.circuitry.and.dielectric.layers—is.prone.to.dam-
age..The.typical.failure.modes.seen.with.temperature.cycling.are.delami-
nation.between.interfaces.or.cracking.somewhere.in.the.die,.whether.it.
be.the.passivation,.the.interlayer.dielectric,.or.through.the.bulk.silicon..
Therefore,.the.chip.metallization.may.see.movement.out.of.position.
Crack
Chip
Die pad
Delamination
Molding compound
Die attach
adhesive
Figure  5.3  Package. material. interfaces. prone. to. delamination. and. subsequent.
package.cracking.(not.to.scale).
Lead frame
Molding compound
Moisture saturation
Pressure
swelling
Internal moisture vaporizes causing cracks
Vapor pocket
delamination
Cracks
Pressure
released
Figure 5.4  Sequence.of.events.during.package.cracking,.or.popcorning,.event.

Page 72
Chapter five: Reliability testing
53
T
a
b
le 5
.5 
K
ey
.P
ro
p
ertie
s.o
f.S
em
ico
n
d
u
cto
r.P
a
ck
a
g
in
g
.M
ateria
ls
Material
Coefficient
of T
hermal
Expansion
(CTE)
(ppm/°C)
Density
(g/cm
3 )
T
hermal
Conductivity
(W/m*K)
Electrical
Resistivity
(µΩ-cm)
T
ensile
Strength
(GP
a)
Melting
P
oint (°C)
Silicon
2.8
2.4
150
N/A
N/A
1430
Molding
.compound
18–65
1.9
0.67
N/A
N/A
165
.(T
g)
Copper
16.5
8.96
395
1.67
0.25–0.45
1083
Alloy-42
4.3
N/A
15.9
N/A
0.64
1425
Gold
N/A
19.3
293
2.2
N/A
1064
Aluminum
23.8
2.80
235
2.7
83
660
Eutectic.tin-lead
.solder
23.0
8.4
50
N/A
N/A
183
Alumina
6.9
3.6
22
N/A
N/A
2050
Aluminum
.nitride
4.6
3.3
170
N/A
N/A
2000
Source:
.A dapted
.
from
.
National.
Semiconductor.
Corporation,.
Data
Sheet:
Semiconductor
Packaging
Assembly
T
echnology
,.August.1999.

Page 73
54
Semiconductor packaging: materials interaction and reliability
5.3.2.1 Package failure modes from temperature
cycling and thermal shock
Temperature.cycling.and.thermal.shock.are.the.cause.of.numerous.failure.
modes.in.semiconductor.packages..Some.of.these.modes.include.broken.
bond.wire.or.lifted.bonds.from.pads,.solder.joint/bump/ball.fatigue.(an.
example.of.which.is.shown.in.Figure 5.5),.cracked.molding.compound,.
and.the.aforementioned.interface.delamination..Related.to.these.issues.is.
the.thermal.expansion.coefficient.and.Young’s.modulus.mismatches.
5.3.2.2 Package failure mode: delamination
Of.the.failure.modes.mentioned,.delamination.is.a.key.concern,.as.it.can.
aid.corrosion.by.creating.one.or.more.pathways.for.moisture.ingress..It.is.
further.discussed.in.Section.5.3.4.
Delamination—or.the.loss.of.adhesion.between.interfaces—is.often.
a.first.step.toward.a.reliability.failure,.whether.it.be.popcorning.or.bond.
wire.lift.or.cracked.silicon..The.causes.are.varied—molding.compound.or.
underfill.shrinkage,.surface.contamination,.and.thermal.stresses,.to.name.
a.few.
With.die.attach.adhesive,.several.failure.modes.are.the.result.of.voids.
or.delamination.in.the.interface.with.the.chip.or.with.the.lead.frame.or.
substrate.pad..Voids.can.result.in.hot.spots.that.could.cause.overheating.
or.thermal.breakdown.of.the.die..Delaminated.areas.may.allow.for.stress.
concentrations,.which.could.result.in.cracked.chips.or.cracks.to.grow.into.
the.molding.compound..Separation.is.often.caused.by.thermal.expansion.
mismatch.stresses.along.the.dissimilar.material.interfaces.
Overall,.the.remedies.are.not.so.simple..Enhancing.adhesion.is.not.
always.straightforward.and.must.be.balanced.against.other.desired.prop-
erties,.similar.to.the.issue.of.corrosion.and.its.possible.solutions.
Solder Ball Joint
Bond pad on chip
Bonding land on substrate
Fatigue
crack
Figure 5.5  A.ductile.solder.fatigue-induced.crack.due.to.temperature.cycling.(not.
to.scale).

Page 74
Chapter five: Reliability testing
55
5.3.3 High-temperature storage life
The.intent.of.the.high-temperature.storage.test.is.to.elicit.premature.bond.
failure,.whether.in.wire.bonds.or.in.flip-chip.bumps..Elevated.tempera-
tures.are.known.to.accelerate.the.typical.failure.mechanisms,.which.usu-
ally.involve.growth.of.brittle.intermetallic.phases.
5.3.3.1 Package failure mode: intermetallics
In. the. case. of. gold. wire. bonding,. it. is. usually. excessive. intermetallic.
growth.between.the.gold.ball.bond.and.aluminum.bond.pad,.which.is.
discussed.further.in.the.chapter.covering.bonding.wires.(see.Chapter.7,.
Section.7.2)..The.intermetallic.layer.can.consume.the.thin.layer.of.alumi-
num,.due.to.the.Kirkendall.effect,.and.is.relatively.porous,.so.bond.resis-
tance. increases. with. time. and. temperature. until. an. electrical. opening.
occurs..Sometimes.this.defect.is.an.intermittent.one,.as.repeated.biasing.
of.the.bad.bond.will.“re-weld”.the.bond.to.the.pad,.at.least.temporarily.
Gold-aluminum.intermetallic.growth.becomes.even.more.accelerated.
in.the.presence.of.halides..And.before.the.advent.of.“green”.or.halogen-
free. materials,. molding. compounds. would. be. the. most. likely. source,.
because. both. bromine. and. antimony. oxides. were. used. as. flame. retar-
dants..Now.that.halogen-free.molding.compounds.will.become.prevalent,.
this.particular.type.of.failure.mechanism.will.likely.disappear.
5.3.4 Temperature-humidity-bias tests
The.purpose.of.subjecting.parts.to.storage.at.85ºC/85%.relative.humid-
ity.and.under.electrical.bias.is.to.ensure.that.the.devices.and.packages.
can. withstand. an. uncontrolled,. moisture-laden. environment. for. an.
extended.period.of.time,.perhaps.as.long.as.their.operating.lives..More.
stressful.versions.of.this.test.are.autoclave.and.highly.accelerated.stress.
test.(HAST).
5.3.4.1 Package failure mode: corrosion
Corrosion.is.the.primary.mechanism.for.failure.with.these.types.of.tests..
The. phenomenon. of. corrosion. is. more. easily. seen. in. a. humid. environ-
ment.than.in.a.dry.one..Thus,.it.is.the.common.failure.mechanism.seen.
in. autoclave,. temperature-humidity. (and. perhaps. with. bias). and. HAST.
test.methods..What.is.typically.observed.is.moisture-induced.corrosion.of.
aluminum.bond.pads.or.interconnects.due.to.the.presence.of.ionic.impuri-
ties.like.chloride,.which.is.shown.in.Figure 5.6..The.ionic.impurities.travel.
to.the.semiconductor.surface.through.diffusion.and.moisture.penetration.
under.these.harsh.test.conditions.
Given.that.plastic.packages.are.nonhermetic,.moisture.absorption.will.
always. be. unavoidable. and. corrosion. will. always. be. a. risk.. Preventing.

Page 75
56
Semiconductor packaging: materials interaction and reliability
corrosion.in.plastic.packages.needs.a.multipronged.approach..Naturally,.
reducing.the.amount.of.ionic.impurities.will.help,.but.it.is.impossible.to.
remove.all.impurities.from.packaging.materials,.and.that.does.not.take.
into.account.any.instance.of.accidental.contamination.through.human.or.
other.errors..Incorporating.ion-getters.into.the.materials.set.may.help.trap.
the.ions,.but.care.must.be.taken.to.ensure.the.getters.do.not.cause.new.
problems..Altering.packaging.materials.to.lower.their.moisture.absorp-
tion. levels. will. help,. but. again. care. must. be. taken. that. other. material.
properties.are.not.altered.detrimentally.
5.4 Limitations of reliability testing
The. intent. of. reliability. tests. is. to. elicit. known. failure. mechanisms.
through.a.set.of.accelerated.tests.and.provide.an.accurate.level.of.field.life.
prediction..However,.not.all.failure.modes.can.be.accounted.for,.due.to.the.
unpredictable.nature.of.things.
Two.kinds.of.failures.are.very.hard.to.predict..One.is.one-off.defects,.
which.can.come.from.unknown.flaws.in.the.chip.or.some.minor.mishap.
during. manufacturing.. Examples. would. be. electrostatic. discharge. and.
particulate.contamination.
Another. type. of. defect. that. would. be. hard. to. detect. by. reliability.
testing. is. an. intermittent. defect.. Marginal. wire. bond. adhesion. or. flip-
chip.connections.are.typical.intermittent.failures,.where.the.failure.may.
“recover”.between.testing.points..In.situ.testing.is.best.at.catching.these.
kinds.of.failures.
Corrosion
Metal lines
Bonding pads
Figure 5.6  Aluminum.bond.pad.corrosion.(not.to.scale).

Page 76
Chapter five: Reliability testing
57
Bibliography
B.. Dipert,. “Silicon. Contends. with. Stuffed. and. Shrinking. Packages,”. EDN,. pp..
49–58,.June.13,.2002.
A..Jalar,.M.F..Rosle,.and.M.A.A..Hamid,.“Effects.of.Thermal.Aging.on.Intermetallic.
Compounds.and.Voids.Formation.in.AuAl.Wire.Bonding,”.Solid State and
Technology,.vol..16,.no..2,.240–246,.2008.
JEDEC,. IPC/JEDEC J-STD-020D.1,. Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices,.March.2008.
JEDEC,.JEP122E: Failure Mechanisms and Models for Semiconductor Devices,.March.2009.
JEDEC,.JEP148A,.Reliability Qualification of Semiconductor Devices Based on Physics of
Failure Risk and Opportunity Assessment,.December.2008.
JEDEC,.JEP150,.Stress-Test-Driven Qualification of and Failure Mechanisms Associated
with Assembled Solid State Surface-Mount Components,.May.2005.
JEDEC,.JEP156: Chip-Package Interaction—Understanding, Identification and Evaluation,.
March.2009.
JEDEC,.JESD22-A101C,.Steady-State Temperature Humidity Bias Life Test,.March.2009.
JEDEC,.JESD22-A104D,.Temperature Cycling,.March.2009.
JEDEC,. JESD22-A110C,. Highly Accelerated Temperature and Humidity Stress Test
(HAST),.January.2009.
JEDEC,. JESD22-A113F,. Preconditioning of Plastic Surface Mount Devices Prior to
Reliability Testing,.October.2008.
JEDEC,.JESD74,.Early Life Failure Rate Calculation Procedure for Electronic Components,.
October.2000.
JEDEC,.www.jedec.org
F.L.A..Latip,.A..Hassan,.and.R..Yahya,.“Delamination.and.Void.Analysis.on.Die.
Attach.Epoxy.of.a.QFN.Package,”.Solid State Science and Technology,.vol..16,.
no..2,.207–213,.2008.
R.H.Y..Lo.and.A.S..Chen,.“Unconventional.Molding.Compounds.for.Conventional.
Packages,”. in. Proceedings FOCUS ’94 Expo and Conference,. San. Jose,. CA,.
August.30–September.1,.1994.
A.F.. Moor,. A.. Casanovas,. and. S.R.. Purwin,. “The. Case. for. Plastic-Encapsulated.
Microcircuits. in. Spaceflight. Applications,”. Johns Hopkins APL Technical
Digest,.vol..20,.no..1,.91–100,.1999.
National.Semiconductor.Corporation,.Data Sheet: Semiconductor.Packaging Assembly
Techonology,.August.1999.
L.T.. Nguyen,. R.H.Y.. Lo,. A.S.. Chen,. H.. Takiar,. and. J.G.. Belani,. “Molding.
Compounds.Trends.in.a.Denser.Packaging.World:.Qualification.Tests.and.
Reliability.Concerns,”.IEEE Transactions on Reliability,.vol..42,.no..4,.518–535,.
December.1993.
L.T.. Nguyen,. A.S.. Chen,. and. R.H.Y.. Lo,. “Interfacial. Integrity. in. Electronic.
Packaging,”. ASME 1995—Application of Fracture Mechanics in Electronic
Packaging and Materials,.EEP-vol..11/MD-vol..64,.35–44,.1995.
Sony.Semiconductor,.Quality and Reliability Handbook, Chapter 2: Failure Mechanisms,.
revised.May.2001.

Page 77

Page 78
section three
Materials used in
semiconductor packaging

Page 79

Page 80
61
chapter six
Polymers
6.1 Molding compounds
6.1.1 Objectives
•. Describe.what.a.molding.compound.is.
•. Convey. its. purpose. and. importance. in. semiconductor. packaging,.
in. regard. to. physical. performance. and. contribution. to. reliability.
assessment.
•. Illustrate.continuous.development.and.improvement.of.this.material.
6.1.2 Introduction
This.chapter.briefly.reviews.the.history.and.use.of.molding.compounds.
in. plastic. semiconductor. packages,. addresses. some. of. the. issues. and.
failure. modes. associated. with. molding. compounds,. and. touches. on.
future.trends.
6.1.3 Background
Molding.compounds.have.been.around.a.very.long.time,.since.the.advent.
of.the.through-hole.plastic.dual-inline.package.(DIP).family.in.the.early.
1970s..Essentially,.molding.compounds.are.epoxy.resins.filled.with.some.
sort.of.silica.filler.to.reduce.the.coefficient.of.thermal.expansion.to.better.
match. that. of. the. lead. frame,. along. with. small. amounts. of. other. addi-
tives,.such.as.carbon.black.for.color.and.bromine.to.act.as.a.flame.retar-
dant..A.comparison.of.the.physical.properties.for.the.various.components.
that.constitute.a.plastic.package.was.previously.given.in.Table 1.3.and.is.
repeated.as.a.refresher.in.Table 6.1.
Initially,. the. predominant. epoxy. compound. used. was. bisphenol-A..
Epoxy.cresol.novolac.replaced.bisphenol-A.as.the.preferred.epoxy.resin.
due.to.its.better.heat.resistance..In.general,.epoxy.resins.became.the.pre-
ferred.backbone.for.molding.compounds.due.to.their.inherent.low.viscos-
ity,.fast.cure.properties,.low.shrinkage.during.cure,.good.adhesion.to.the.
other.components.in.a.chip.package,.and.good.overall.mechanical.stabil-
ity..Both.epoxy.cresol.novolac.and.bisphenol-A.produce.sodium.chloride.
as.by-products.during.synthesis..Because.both.elements.are.detrimental.

Page 81
62
Semiconductor packaging: materials interaction and reliability
to.integrated.circuit.(IC).reliability,.care.must.be.taken.to.remove.them.
from.the.final.resin.product.before.molding.compound.formulation.
The. filler. comes. in. the. form. of. amorphous. or. crystalline. silica..
Sometimes.alumina.is.used.as.the.filler.for.increased.thermal.conductiv-
ity.and.high.heat.dissipation.properties,.but.it.is.very.abrasive.compared.
to. silica.. Amorphous. silica. is. preferred. when. a. low. thermal. expansion.
coefficient.is.needed,.and.crystalline.silica.provides.some.thermal.conduc-
tivity.at.the.expense.of.a.higher.coefficient.of.thermal.expansion..In.an.
epoxy.cresol.novolac–based.compound,.the.filler.makes.up.65%.to.75%.by.
weight,.with.the.resin.constituting.the.majority.of.the.balance..Fillers.pro-
vide.mechanical.strength.to.the.compound.and.reduce.the.thermal.expan-
sion.coefficient,.which,.in.turn,.reduces.shrinkage.after.molding..Fillers.do.
have.one.major.risk,.in.that.silica.may.contain.minute.amounts.of.uranium.
and.thorium,.which.generate.αあるふぁ-particles.and.are.known.to.cause.soft.errors.
in.sensitive.circuitry,.like.dynamic.random.access.memory.(DRAM).cells.
To.complete.the.molding.compound.formulation,.small.amounts.of.
pigments,.coupling.agents,.mold.release.agents,.reaction.accelerators,.anti-
oxidants,.water.getters,.plasticizers,.and.flame.retardants.are.all.added..
Coupling.agents.increase.resin.adhesion.to.the.fillers,.the.chip,.and.the.lead.
frame..Mold.release.agents.do.just.that:.help.free.the.molded.part.from.the.
mold.chase..Flame.retardants.are.a.necessary.requirement.for.the.plastic.
Table 6.1  Key.Properties.of.Semiconductor.Packaging.Materials
Material
Coefficient
of Thermal
Expansion
(CTE)
(ppm/°C)
Density
(g/cm3)
Thermal
Conductivity
(W/m*K)
Electrical
Resistivity
(µΩ-cm)
Tensile
Strength
(GPa)
Melting
Point
(°C)
Silicon
2.8
2.4
150
N/A
N/A
1430
Molding.
compound
18–65
1.9
0.67
N/A
N/A
165.(Tg)
Copper
16.5
8.96
395
1.67
0.25–
0.45
1083
Alloy-42
4.3
N/A
15.9
N/A
0.64
1425
Gold
N/A
19.3
293
2.2
N/A
1064
Aluminum
23.8
2.80
235
2.7
83
660
Eutectic.
tin-lead.
solder
23.0
8.4
50
N/A
N/A
183
Alumina
6.9
3.6
22
N/A
N/A
2050
Aluminum.
nitride
4.6
3.3
170
N/A
N/A
2000
Source: .A dapted. from. National. Semiconductor. Corporation,. Data Sheet: Semiconductor
Packaging Assembly Technology,.August.1999.

Page 82
Chapter six: Polymers
63
package. to. meet. the. industry. flammability. standard. of. Underwriters.
Laboratories’.(UL).standard.94.V-0,.and.until.very.recently,.the.standard.
was.met.by.the.use.of.brominated.epoxy.and.antimony.trioxide.
The. properties. of. a. molding. compound. are. a. balance. between. its.
moldability. in. a. high-volume. automated. manufacturing. environment.
and.its.relationship.to.the.overall.package’s.performance.and.reliability..
The.coefficient.of.thermal.expansion.is.considered.a.good.marker.that.cor-
relates.to.the.projected.reliability,.as.it.is.a.marker.of.the.mechanical.qual-
ity.of.the.package.and.its.ability.to.withstand.thermal.stresses..Flexural.
modulus.of.the.compound.is.next.in.importance.when.it.comes.to.reliabil-
ity,.as.it.indicates.the.amount.of.“give”.the.compound.has.in.the.presence.
of.mechanical.or.thermal.stress.
Table 6.2  Influence.of.Molding.Compound.Ingredient.on.Physical.Properties
Ingredients
Property
Filler
(>70%)
Epoxy
(~10%)
and
Hardener
(~7%)
Elastomer.
(<5%)
Catalysts
Flame
Retardants
and
Scavengers
Waxes
and
Oils
Viscosity.
(rheology)
–.–.–
+++
–.–.–
Cure.rate.
(productivity)
+++
+++
Mold.cleanliness
0
00
Mold.release
–.–.–
–.–
+++
Stress.in.device
+
+++
Glass.transition.
temperature.(Tg)
0
Strength
++
0
Moisture.
absorption
+++
–.–.–
0
0
Thermal.
conductivity
+++
Combustability
+++
+++
Electrical.
reliability
+
0
0
0
Notes: +,. positive. influence;. +++,. strongest. positive. influence;. –,. unfavorable;. 0,. either.
favorable.or.unfavorable..This.table.provides.a.quick.overview.of.the.composition.
of.typical.epoxy.molding.compounds.(EMCs).by.major.components.and.the.effect.
that.each.of.these.components.has.on.the.key.performance.properties.(molding.and.
cured.properties).
Source: .A dapted. from. Richard. C.. Benson,. Dawnielle. Farrar,. and. Joseph. A.. Miragliotta,.
Johns Hopkins APL Technical Digest,.28(1),.58–67,.2008.

Page 83
64
Semiconductor packaging: materials interaction and reliability
In.summary,.Table 6.2.shows.how.much.effect.each.ingredient.in.a.
molding.compound.has.on.the.overall.material.performance.and.behav-
ior..As.noted.in.the.table,.several.key.properties.of.the.cured.compound.
are.attributable.to.the.filler.particles..The.selection.of.filler.type.by.mate-
rial,.size,.and.shape.will.control.end.parameters.such.as.thermal.expan-
sion,.moisture.absorption,.thermal.conductivity,.and.strength.
6.1.4 Newer formulations
As. already. mentioned,. epoxy. cresol. novolac. was. the. backbone. of. most.
molding. compounds. until. the. 1990s.. Then,. with. the. use. of. larger. and.
larger.surface-mount.packages.and.the.advent.of.ball.grid.arrays.and.all.
of.their.attendant.issues,.new.chemistries.and.formulations.were.required.
to.meet.their.manufacturing.and.reliability.needs.
6.1.4.1 Biphenyl
Biphenyl. resins. turned. out. to. be. the. successful. approach. for. reducing.
moisture.uptake.in.compounds.and.increased.resistance.to.popcorning.
(see.Section.6.3.9)..The.reason.was.due.to.the.nature.of.biphenyl.resins.that.
they.could.be.loaded.up.with.silica.filler,.to.nearly.90%.by.weight..That.
way,.there.was.hardly.any.organic.material.available.to.absorb.moisture..
The.chemical.structure.is.shown.in.Figure 6.1.
The. possible. disadvantage. with. biphenyl. resins. is. their. low. glass.
transition.temperature,.typically.around.125ºC..It.was.feared.that.a.given.
package.using.a.biphenyl-based.molding.compound.would.most.likely.
be.subject.to.a.coefficient.of.thermal.expansion.(commonly.denoted.as.αあるふぁ2).
above.the.glass.transition.temperature.during.subsequent.thermal.pro-
cessing. and. reliability. testing..αあるふぁ2. nearly. always. imposes. a. greater. level.
of.mechanical.stress.on.a.package..However,.it.turned.out.in.numerous.
evaluations. and. field. use. that. such. fears. about. biphenyl. molding. com-
pounds.were.unfounded,.and.these.molding.compounds.were—and.still.
are—used.commercially.
CH3
CH3
CH3
CH3
CH2CHCH2O
O
OCH2CHCH2
O
Figure 6.1  Chemical.structure.of.biphenyl.resin.

Page 84
Chapter six: Polymers
65
6.1.4.2 Multifunctional
Initially. utilized. to. help. resolve. the. popcorn. package. cracking. issue,.
multifunctional.resins.have.a.high.glass.transition.temperature.(around.
220ºC).due.to.high.cross-linking.density..The.resin.structure.is.shown.
in.Figure 6.2..The.cross-linking.density.was.thought.to.increase.high.
temperature.strength.but.turns.out.it.also.increases.the.resin’s.ability.
to. absorb. moisture.. Therefore,. multifunctional-based. molding. com-
pounds.turned.out.to.be.unsuccessful.in.combating.the.popcorn.crack-
ing.issue.
However,. it. turns. out. that. multifunctional. compounds. reduced.
the. substrate. package. warpage. issue,. apparently. because. their. high.
glass. transition. temperature. meant. the. molding. compound. underwent.
less. distortion. than. formulations. with. lower. transition. temperatures..
Multifunctional-based. molding. compounds. remain. in. commercial. use.
for.many.types.of.substrate-based.semiconductor.packages.
6.1.4.3 Aromatic resins
With.the.requirement.for.environmentally.friendly.molding.compounds.
(see.Section.6.1.7.1),.the.resin.backbone.for.molding.compounds.needed.to.
change.again..Examples.of.alternate.resin.structures.that.do.not.require.
bromine.or.antimony.as.flame.retardants.are.shown.in.Figure 6.3..Many.
CH
n
H
O
OCH2CHCH2
OCH2CHCH2
OCH2CHCH2
O
O
Figure 6.2  Chemical.structure.of.multifunctional.resin.

Page 85
66
Semiconductor packaging: materials interaction and reliability
of.these.new.organic.materials.are.proprietary,.and.it.is.difficult.to.find.
much.public.information.about.their.behavior.
6.1.5 Technology challenges
As.packaging.and.manufacturing.technology.and.processes.have.changed.
over.the.years,.so.have.the.formulations.and.behaviors.of.molding.com-
pounds.to.meet.the.needs.of.continued.high-volume.production.
6.1.5.1 Moldability
Transfer.molding.is.the.means.of.encapsulating.the.chip..Improving.the.
moldability.of.a.molding.compound.means.controlling.the.viscosity.and.
velocity.of.the.melted.compound.before.it.sets.up.and.hardens..Controlling.
H
CH2
CH2
CH2
CH2
OH
n
OH
H
n
OH
OH
Figure 6.3  Examples.of.chemical.structures.for.aromatic.resins.
Time
Temperature
A
Temperature
B
TA > TB
Viscosity
Figure 6.4  Viscosity.curve.versus.time.and.under.the.influence.of.temperature.

Page 86
Chapter six: Polymers
67
these.two.variables.is.made.more.difficult.due.to.the.fact.that.molding.
compounds. are. non-Newtonian. fluids;. therefore,. the. fluid. mechanics.
going.on.inside.a.mold.chase.are.very.complex..Figure 6.4.illustrates.the.
behavior.of.viscosity.over.time.as.the.molding.compound.undergoes.heat.
and.pressure.during.the.transfer.molding.process.
The. two. factors. must. also. be. balanced. between. the. need. for. high.
through-put.while.not.sending.the.liquid.compound.through.the.mold.
with.too.much.force.and.thus.damaging.the.chip.surface,.or.deforming.
the.lead-frame.lead.tips.or.sweeping.away.the.bonding.wires.
Over.time,.the.designs.of.mold.chases.have.changed,.going.from.a.
single,. large-volume. transfer. pot. into. multiple. cavities. and. runners. to.
multiple,.small-volume.pot.designs.with.short.runners.and.few.or.two.
cavities.to.fill..Those.changes.also.required.tweaks.to.formulations.
6.1.5.2 Glass transition temperature
The.glass.transition.temperature.(Tg).represents.the.softening.point.of.an.
adhesive..To.measure.that.transition.point,.a.differential.scanning.calo-
rimetry.(DSC).test.system.shows.the.peak.exothermic.reaction.tempera-
ture.for.a.given.polymer.system..Further.information.on.DSC.is.given.in.
Section.6.2.and.in.Appendix.B.
6.1.5.3 Flexural modulus
The.flexure.test.is.a.measure.of.the.behavior.of.materials.under.simple.
beam. loading. or. bending.. Maximum. stress. and. strain. over. increas-
ing.loads.are.measured.and.plotted.in.a.stress–strain.diagram..Flexural.
strength.is.defined.as.the.maximum.stress.endured.in.the.outermost.fiber.
of.the.material,.which.is.calculated.at.the.test.specimen.surface.on.the.con-
vex.or.tension.side..Flexural.modulus.comes.from.calculating.the.slope.of.
Strain, %
Stress, MPa
Figure 6.5  Stress–strain.curve.

Page 87
68
Semiconductor packaging: materials interaction and reliability
the.stress.versus.the.deflection.curve..Figure 6.5.shows.the.stress–strain.
curve.from.flexure.testing.
Flexure.testing.is.typically.done.on.relatively.flexible.materials,.like.
polymers,. wood,. and. composites—which. would. include. molding. com-
pounds.. Test. methods. include. three-point. flex. and. four-point. flex.. The.
three-point.flex.example.is.shown.in.Figure 6.6,.as.this.test.method.is.most.
commonly.used.for.polymers..In.a.three-point.test,.the.area.of.uniform.
stress.is.rather.small.and.concentrated.under.the.center.loading.point.
6.1.5.4 Coefficient of thermal expansion
As.stated.earlier,.epoxy.alone.has.a.very.high.coefficient.of.thermal.expan-
sion,. around. 80. ×. 10–6/ºC,. compared. to. the. silicon. chip. or. copper. lead.
frame.or.organic.substrate..Filling.the.epoxy.with.silica.filler.brings.down.
the.thermal.expansion.coefficient.into.the.teens,.which.would.match.the.
lead.frame.or.substrate.but.would.still.be.high.compared.to.silicon..Using.
biphenyl.or.similar.epoxy.types.allows.more.filler.to.be.added.and.brings.
the.coefficient.down.to.the.high.single.digits.but.still.not.as.low.as.silicon,.
which.is.about.3.×.10–6/ºC.
Also,.the.glass.transition.temperature.marks.the.point.where.the.ther-
mal.coefficient.increases.significantly..Excursions.into.elevated.tempera-
tures.may.result.in.higher-than-anticipated.stresses.on.the.package.and.
the.device..The.change.of.thermal.expansion.with.temperature.is.illus-
trated.in.Figure 6.7.
In.short,.a.molding.compound’s.coefficient.of.thermal.expansion.is.a.
tricky.balancing.act.with.the.other.components.that.make.up.a.semicon-
ductor.package.and.the.chip.
6.1.5.5 Stress index
This.semiquantitative.measure.is.generally.used.as.an.indicator.for.mold-
ing.compound.and.the.level.of.stress.induced.by.the.nature.of.the.mate-
rial..The.stress.index.is.defined.as.“E.times.CTE,”.or.flexural.modulus.
multiplied.by.coefficient.of.thermal.expansion.
Force
Flexural test with three-point loading
Figure 6.6  Flexural.stress.test.using.three-point.loading.

Page 88
Chapter six: Polymers
69
Stress. indices. are. generally. useful. as. a. comparison. tool,. to. rank.
various.kinds.of.molding.compounds.for.the.levels.of.stress.each.might.
induce.on.a.package.and.the.die.within..Lowering.the.stress.in.a.molding.
compound.involves.meeting.two.opposing.demands—lowering.the.coef-
ficient.of.thermal.expansion.and.lowering.the.compound’s.modulus..To.
lower.the.thermal.expansion.coefficient.is.to.increase.filler.concentrations.
in. the. molding. compound,. which. has. the. unfortunate. effect. of. raising.
the. flexural. modulus.. Lowering. the. flexural. modulus. is. not. so. simple,.
but.that.usually.involves.altering.the.resin.and.hardener.chemistry,.mak-
ing.for.more.flexible.polymer.chains..However,.those.chemical.changes.
are.usually.not.enough.to.offset.the.high.levels.of.filler.required.to.lower.
thermal.expansion.
6.1.6 Failure modes associated with molding compounds
Along.with.the.aforementioned.issues.with.new.flame.retardant.materi-
als,.the.most.prominent.issue.associated.with.molding.compound.is.sol-
der.reflow.package.cracking,.otherwise.known.as.popcorning.
6.1.6.1 Package cracking during solder reflow
As.discussed.in.Chapter.3,.when.large.and.thin.(3-mm.thick.and.below).
surface-mount. packages. (such. as. quad. flat. packs. and. plastic. leaded.
chip. carriers,. and. later,. plastic. ball. grid. arrays). became. prevalent. in.
the.late.1980s,.the.phenomenon.named.popcorning.became.well.known..
Popcorning. occurs. when. a. moisture-filled. plastic. package. undergoes.
Temperature, °C
δでるた, Displacement
Tg,
glass
transition
temperature
αあるふぁ1
αあるふぁ2
Plastic expansion curve
Figure 6.7  Change.in.coefficient.of.thermal.expansion.with.temperature.

Page 89
70
Semiconductor packaging: materials interaction and reliability
the.solder.reflow.process.in.an.in-line.oven..The.moisture.often.pools.
in. areas. of. weakened. adhesion,. which. eventually. causes. delamina-
tion.. The. package. is. subjected. to. rapid. heating. to. temperatures. above.
the. boiling. point. of. water.. Therefore,. the. moisture. inside. the. package.
turns.to.steam.and.exerts.pressure.to.escape..The.molding.compound.
typically. cannot. withstand. the. force. and. commonly. fails. through. the.
backside,.resulting.in.an.external.crack..The.sound.of.the.package.failing.
is.said.to.sound.like.popcorn.popping,.and.hence.the.term.popcorning..
The.sequence.of.events.was.shown.in.Figure 5.4.and.is.repeated.again.
Lead frame
Molding compound
Moisture saturation
Pressure
swelling
Internal moisture vaporizes causing cracks
Vapor pocket
delamination
Cracks
Pressure
released
Figure 6.8  Sequence.of.events.during.package.cracking,.or.popcorning,.event.
Crack
Chip
Die pad
Delamination
Molding compound
Die attach
adhesive
Figure  6.9  Package. material. interfaces. prone. to. delamination. and. subsequent.
package.cracking.(not.to.scale).

Page 90
Chapter six: Polymers
71
in.Figure 6.8,.and.Figure 6.9.(once.again.from.Figure 5.3).shows.the.end.
result.of.popcorning.
A. standard—the. IPC-SM-786A—was. created. by. the. IPC®. (formerly.
the. Institute. for. Interconnecting. and. Packaging. Electronic. Circuits). to.
control.moisture.levels.in.semiconductor.packages.prior.to.solder.reflow..
The.specification,.now.superseded.by.J-STD-020.and.J-STD-032,.specified.
storage.conditions.and.the.need.for.dry-packing.or.even.baking.before.
reflow.for.very.sensitive.packages.
Still,.there.was.great.interest.into.the.1990s.to.discover.chemistries.
that.could.make.molding.compounds.that.were.less.moisture.sensitive..
Research.in.this.area.led.to.the.development.and.use.of.biphenyl-based.
molding.compounds.
6.1.6.2 Substrate postmold warpage
With.the.advent.of.plastic.ball.grid.arrays.and.other.substrate-based.plastic.
semiconductor.packaging,.another.issue.arose,.that.of.substrate.warpage,.
and.not.subtle.or.slight.concave.or.convex.curvature,.but.readily.obvious.
to.the.naked.eye,.as.shown.in.Figure 6.10..What.can.be.more.alarming.
is.that.the.type.of.curvature.will.change.depending.on.the.temperature.
and.thermal.processing..In.all,.such.a.high.level.of.warpage.and.cycling.
between.negative.and.positive.modes.naturally.exerts.unwanted.stresses.
on.the.package,.affecting.performance.and.reliability.
Causes.are.multiple,.but.they.include.the.fact.that.organic.substrates.
are.much.less.rigid.than.metallic.lead.frames.and.that.molding.compound.
is.applied.to.only.one.side.of.the.substrate..The.thermal.and.mechanical.
“Smile”
(a)
“Frown”
(b)
Figure  6.10  (a). Concave. curvature. (“smile”). of. substrate. and. package. (not. to.
scale)..(b).Convex.curvature.(“Frown”).of.substrate.and.package.(not.to.scale).

Page 91
72
Semiconductor packaging: materials interaction and reliability
properties.of.the.molding.compound.need.to.be.in.better.balance.with.the.
properties.of.the.other.packaging.materials.
6.1.7 Future developments
Just.as.package.technology.undergoes.continual.changes.and.new.types.
of.packages.are.developed,.the.properties.and.characteristics.of.the.mold-
ing.compounds.used.to.encapsulate.them.evolve.
6.1.7.1 “ Green” molding compounds and changes
to flame retardant additives
The.push.for.“green”.or.environmentally.friendly.materials.received.a.big.
impetus. from. the. effect. of. environmental. regulation. on. electronic. sys-
tems,.specifically.with.the.RoHS.(Restriction.of.Hazardous.Substances).
directive.adopted.by.the.European.Union.in.February.2003,.which.came.
into.force.in.July.2006..This.directive.directly.affected.molding.compound.
composition.due.to.its.regulation.about.the.levels.of.bromine.allowed.
For. some. background,. to. meet. Underwriters. Laboratories’. flamma-
bility.standard.V-0,.molding.compounds.traditionally.employed.bromi-
nated. epoxy. resins. and. antimony. oxides. as. flame. retardants.. But. with.
the. amount. of. organic. compounds. with. bromine. restricted,. molding.
compound. formulators. had. to. come. up. with. alternate. flame. retardant.
solutions.
The.road.to.create.molding.compounds.that.meet.these.new.environ-
mental.regulations.has.not.been.without.its.bumps..Sumitomo.Bakelite,.
a.leading.supplier.of.molding.compound,.first.used.coated.inorganic.red.
phosphorus.particles.as.substitute.flame.retardant.material.in.its.EME-U.
family.of.“green”.molding.compounds.during.the.late.1990s.(the.coating.
of.aluminum.hydroxide.and.phenol.resin.was.necessary.to.prevent.the.
diffusion.of.red.phosphorus.ions.throughout.the.compound)..Otherwise.
the.new.compounds.met.all.the.mechanical,.physical,.and.reliability.crite-
ria.necessary.for.a.production-worthy.product.
However,. after. less. than. a. year. of. field. use. (in. some. cases,. only. a.
few. weeks),. devices. packaged. with. the. new. formulation. began. to. fail..
The. most. common. failure. mode. identified. was. resistive. short. and. cur-
rent.leakage.between.adjacent.internal.leads..Often,.the.failures.appeared.
intermittently,. and. seemed. to. be. dependent. on. humidity,. voltage,. and.
temperature..Another.failure.mode.seen.was.increased.resistance.or.an.
open.circuit.due.to.wire.bond.failures.
Extensive.failure.analysis.revealed.the.phosphoric.acid.caused.cop-
per. and. silver. migration. and. filament. growth,. causing. shorts. between.
the. leads.. As. it. turns. out,. the. coating. around. the. red. phosphorus. was.
either. too. thin. or. not. sturdy. enough. to. withstand. all. the. process. and.

Page 92
Chapter six: Polymers
73
manufacturing.steps..The.aluminum.hydroxide.coating.could.degrade.in.
the.presence.of.moisture.and.oxygen.during.elevated.temperatures,.thus.
converting.into.alumina.and.water.as.shown.in.Equation.(6.1):
.
2Al(OH)3.→.3H2O.+.Al2O3.
(6.1)
The.resulting.phosphoric.acid.now.acts.like.an.electrolyte,.allowing.for.
copper. and. silver. migration,. especially. if. adjacent. leads. are. electrically.
biased..The.process.is.illustrated.in.Figure 6.11..It.was.also.found.that.an.
excess.of.phosphoric.ions.probably.contributed.to.accelerated.ball.bond.
pad.intermetallics.and.corrosion,.leading.to.the.wire.bond.failures.
In.turn,.the.release.of.phosphorus.ions.(PO4).is.also.increased.in.the.
same. presence. of. elevated. temperatures. and. increased. moisture.. Such.
elevated. temperatures. occur. normally. during. manufacturing,. like. at.
the.transfer.molding.step.as.well.as.at.solder.reflow..With.the.increased.
oxygen.and.water.present,.the.phosphorus.ions.are.converted.into.acids,.
as.seen.in.Equation.(6.2):
.
4P.+.5O2.+.6H2O.→.4H3PO4.
(6.2)
In.the.end,.red.phosphorus.proved.not.to.be.the.solution.to.the.“green”.
flame.retardant.issue,.as.it.proved.too.reactive.in.the.typical.environment.
seen.by.plastic.semiconductor.packages..The.coatings.solution.to.prevent.
reactivity.ended.up.not.being.effective.enough.
Although.red.phosphorus.proved.disastrous,.current.“green”.mold-
ing.compound.formulations.use.other.proprietary.solutions,.such.as.tran-
sitional.metal.oxides.
+
+
+
+
Lead +
(Anode)
Lead +
(Anode)
Lead –
(Cathode)
Lead –
(Cathode)
Red P and
P acids
Cu Cu2+ + 2e
Cu2+ + 2e
Cu
Ag Ag+ + e
Ag+ + e Ag
Cu, Ag
+
+
+
+
Cu/Ag
Figure 6.11  Red.phosphorous.and.phosphoric.acid.acting.as.a.catalyst.for.copper.
and.silver.migration.between.lead.frame.leads.(not.to.scale).

Page 93
74
Semiconductor packaging: materials interaction and reliability
6.1.7.2 Molded underfill
This.product.aims.to.combine.the.manufacturing.and.physical.proper-
ties. of. a. compound. with. that. of. flip-chip. underfills.. Although. the. two.
products.have.many.similarities.in.chemistry.and.composition,.their.pur-
poses,.and.therefore.behaviors,.are.different..It.has.proven.tricky.to.match.
the.two.primary.purposes—fully.filling.the.gap.between.chip.and.sub-
strate.with.good.moldability.in.high-volume.production.
More. details. about. the. progress. in. molded. underfills. will. be. dis-
cussed.in.Section.6.3.
6.1.7.3 High-density packaging
High-density.packaging.refers.to.packages.with.multiple.chips,.whether.
side-by-side. or. stacked. on. top. of. one. another.. For. complex. structures.
involving. multiple. chips. and. multiple. levels. of. wire. bonding,. there. is.
the.risk.of.excessive.wire.sweep.and.subsequent.yield.loss..Some.level.of.
wire.sweep.could.be.mitigated.by.optimizing.the.layout.of.the.bonding.
wires,.but.careful.selection.of.a.molding.compound.formulation.is.also.
necessary.. In. addition. to. any. changes. to. molding. compound. to. reduce.
wire.sweep.even.further,.usually.by.going.to.very.low.viscosity.formula-
tions,.there.may.be.changes.necessary.to.the.mechanical.aspect.of.mold-
ing,.such.as.the.mold.chase.design.or.even.moving.away.from.traditional.
transfer.molding.methods.altogether.
One.such.change.to.the.mold.chase.design.is.going.from.the.conven-
tional.bottom-gate-in-the-corner.design.to.a.top-gate.or.center-gate.design,.
as.shown.in.Figure 6.12..A.radial.mold.flow.from.a.top.gate.could.minimize.
Side gate
Top gate
Bottom gate
Figure 6.12  Comparison.of.mold.gate.placement.

Page 94
Chapter six: Polymers
75
wire.sweep.and.reduce.filler.separation,.which.can.occur.when.the.fine.pitch.
bonding.wires.filter.out.fillers.as.the.molding.compound.moves.between.
them..This.becomes.more.and.more.of.a.problem.as.the.wire.lengthens.
Another.solution.may.be.dispensing.an.encapsulant.over.the.wires.
prior. to. the. molding. step,. in. order. to. “lock. down”. the. wires. in. place..
However,.that.adds.a.few.more.process.steps.to.the.manufacturing.flow,.
which.tends.to.be.undesirable.to.through-put.and.cost.but.could.be.justi-
fied.with.higher.yield.
Some.alternate.methods.to.transfer.molding.might.be.liquid.molding,.
compression.molding,.and.transfer.molding.with.vacuum.assist..These.
alternate.processes.remain.in.the.developmental.stage.
6.1.7.4 Compatibility with copper wire bonding
With.the.high.price.of.gold.(hovering.near.$1,000.per.ounce).becoming.a.
norm,.back-end.operations.for.semiconductor.packaging.are.looking.to.
substitute.copper.wire.for.the.wire.bonding.step,.as.a.cost-control.mea-
sure..The.advantages.and.disadvantages.of.copper.wire.versus.gold.are.
examined.in.detail.in.Section.6.2.
Here,. the. discussion. focuses. on. how. the. change. in. bonding. wire.
changes. the. performance. requirements. of. the. molding. compound.. For.
instance,. recent. studies. point. toward. more. careful. control. of. chloride.
levels.to.ensure.a.reliable.package.when.exposed.to.moisture..(There.are.
some.indications.that.perhaps.pH.levels.also.need.to.be.controlled,.but.
this.has.not.yet.been.confirmed.).Copper.behaves.differently.when.bond-
ing.onto.aluminum.bond.pads..In.general,.copper.is.more.reactive.than.
gold.and.corrodes.more.easily..Apparently.the.copper–aluminum.bond.
interface.is.very.suscepti