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Acknowledgments.
People that the author would like to thank for their assistance in the creation of his book are mentioned.
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Chapter 1: Introduction.
An introduction to the book "FPGA Architecture: Survey and Challenges" is presented.
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Chapter 1: Introduction.
Chapter 1 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It discusses advantages of asynchronous design and presents reasons why asynchronous design has been avoided by system and digital circuit designers so far. It also discusses asynchronous design based on industrial-quality flows and tools. It views asynchronous design as a method to introduce feedback control for synchronization of latches and flip flops in a digital design.
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Chapter 1: Introduction.
The article discusses various reports published within the issue, including one on the alternatives to the conventional paradigm of network design, one on designing Network-on-Chip (NoC) architectures under Markovian assumption, and one on the new problems in network design.
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Chapter 2: Deterministic Perspective.
The article explores the major approaches proposed in a deterministic setup for system-level design. It cites the formulation of the problem of network design as a mathematical program aiming the determination of one or more of the unknowns such as mapping, scheduling and topology. A graph-based formalism for the network design is also discussed.
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Chapter 2: Early History of Programmable Logic.
Chapter 2 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the origins of the contemporary Field-Programmable Gate Array (FPGA) as well as the development of early programmable devices. It also highlights the introduction of a series of read-only memory (ROM)-based programmable devices. Moreover, the proposal of the first static memory-based FPGA is discussed.
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Chapter 2: Handshake Technology.
Chapter 2 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It discusses the Handshake Technology design flow, which primarily aims at providing the Integrated Community access to the clockless circuit technology. It provides dedicated tools and representations developed for the Handshake Technology design flow. It explores innovative aspects of the Handshake Technology design flow and addresses it's dedicated asynchronous representations and tools.
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Chapter 3: Programming Technologies.
Chapter 3 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the underlying programming technology that is used to control the programmable switches that give field-programmable gate arrays (FPGAs) their programmability. It also highlights various modern programmable technologies and their significant effect on programmable logic architecture. Moreover, the advantages and disadvantages of static memory-based programming are discussed.
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Chapter 3: Stochastic Perspective.
The article offers information on the probabilistic approach in designing Network-on-Chip (NOC) architectures under Markovian assumption. It keys out the two main problems within the approach and the application, performance, and various power/energy metrics that need to be replaced by probability distributions and their corresponding moments. From the analysis, it is determined that probabilistic approaches can better describe the distributed computational processes mapped in NoC architecture.
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Chapter 3: Synchronous-to-asynchronous RTL Flow Using NULL Convention Logic (NCL).
Chapter 3 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It discusses the synchronous to asynchronous reimplementation of synchronous (RTL) flow using Null Convention Logic (NCL). It presents observations on which the applicability of synchronous RTL compilers to NCL flow is based. It explains the functioning of NCL and presents observations that reduce the complexity of the delay-insensitive analysis of NCL systems.
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Chapter 4: De-synchronization: A Simple Mutation to Transform a Circuit into Asynchronous.
Chapter 4 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It discusses the strategy of de-synchronization, which mimics synchronous circuit without a clock and substitutes the clock with an asynchronous control layer. It presents a formal model that specifies asynchronous controllers called Signal Transition Graph. It provides the minimum requirements for an asynchronous scheme to implement correct data transfers between latches.
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Chapter 4: Logic Block Architecture.
Chapter 4 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the role of programmable logic blocks in field programmable gate arrays (FPGAs). It highlights the trends in logic block architecture as well as the issues that involve programmable routing circuit design and architecture. Moreover, the basic trade-offs in logic block architecture design and the nomenclature needed to describe it are discussed.
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Chapter 4: Statistical Physics Perspective.
The article presents a statistical physics inspired traffic analysis and major approaches proposed about the complexity of networked architectures. It discusses the different approaches being employed for modelling and analyzing network performance such as the schematic representation of a Virtual Random Growing Network (VRGN), statistical approach to load distribution, and a randomized heuristic. Fundamental problems in the field of network design are also identified.
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Chapter 5: Automated Gate Level Pipelining (Weaver).
Chapter 5 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It discusses a translation approach in which conventional re-implementations of synchronous designs are automatically implemented as fine grain pipelined asynchronous quasi-delay-insensitive circuits. It explains the inefficiency of fine grain pipelining in synchronous systems with the help of an example with retiming based automated synchronous pipelining.
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Chapter 5: Routing Architecture.
Chapter 5 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the role of programmable routing in the field programmable gate array (FPGA). It highlights the common characteristics of logic circuits that influence the architecture of FPGA routing. Moreover, issues concerning the design of interconnect networks in routing architecture are discussed.
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Chapter 6: Applications and Success Stories.
Chapter 6 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It illustrates techniques using realistic examples such as low-power robust design using de-synchronization. It considers standard components, to show the advantages of asynchronous implementations to all kinds of applications and domains. It also discusses cell customization and security benefits, and the resistance of cryptographic coprocessor design to multiple side-channel attacks.
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Chapter 6: Input/Output Architecture and Capabilities.
Chapter 6 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the ability of input/output (I/O) pads and cells to connect on field programmable gate arrays (FPGAs). It also discusses architecture-level issues and features in the design of I/O cells. Moreover, issues surrounding the supporting logic and circuitry in the I/O cell design are considered.
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Chapter 7: Conclusions.
Chapter 7 of the book "Foundations and Trends in Electronic Design Automation," vol. 2, is presented. It presents approaches that are based on asynchronous reimplementation of synchronous designs or the synchronous-asynchronous direct translation flow (SADT). It discusses the flows that make asynchronous design as simple as the synchronous Register Transfer Level flow. It establishes the general principles of SADT methodology and presents its advantages such as low power and security.
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Chapter 7: Improving FPGAs.
Chapter 7 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the role of the field programmable gate array (FPGA) architectural developments in improving the area efficiency, performance and power consumption of FPGAs. It also examines the gap between FPGAs and application-specific integrated circuits (ASICs) to be able to describe the alternatives for the improvement of FPGAs.
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Chapter 8: Emerging Challenges and Architectures.
Chapter 8 of the book "FPGA Architecture: Survey and Challenges" is presented. It explores the challenges and potential approaches for field programmable gate arrays (FPGAs). It also examines new architectures that are considered in the increasing levels of integration and issues that will be faced when improvements from complementary metal oxide semiconductors (CMOS) become more limited. Moreover, issues concerning the impact of continued scaling of CMOS processes on FPGA users are discussed.
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Design Automation of Real-Life Asynchronous Devices and Systems.
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.ABSTRACT FROM AUTHORCopyright of Foundations &Trends in Electronic Design Automation is the property of Now Publishers and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.
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FPGA Architecture: Survey and Challenges.
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.ABSTRACT FROM AUTHORCopyright of Foundations &Trends in Electronic Design Automation is the property of Now Publishers and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.
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References.
References for the articles published in the book "FPGA Architecture: Survey and Challenges" are presented.
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References.
A list of articles related to asynchronous design that were published in several journals is presented including "Optimum Power: Performance Pipeline Depth," by A. Hartstein and T. R. Puzak and "Computer Architecture: A Quantitative Approach," by J. L. Hennessy and D. Patterson.
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The Chip Is the Network: Toward a Science of Network-on-Chip Design.
In this survey, we address the concept of network in three different contexts representing the deterministic, probabilistic, and statistical physics-inspired design paradigms. More precisely, we start by considering the natural representation of networks as graphs and discuss the main deterministic approaches to Network-on-Chip (NoC) design. Next, we introduce a probabilistic framework for network representation and optimization and present a few major approaches for NoC design proposed to date. Last but not least, we model the network as a thermodynamic system and discuss a statistical physics-based approach to characterize the network traffic. This formalism allows us to address the network concept in the most general context, point out the main limitations of the proposed solutions, and suggest a few open-ended problems.ABSTRACT FROM AUTHORCopyright of Foundations &Trends in Electronic Design Automation is the property of Now Publishers and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.
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Thermally Aware Design.
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, thermal issues have come to the forefront, and thermally aware design techniques are likely to play a major role in the future. While improved heat sink technologies are available, economic considerations restrict them from being widely deployed until and unless they become more cost-effective. Low power design is helpful in controlling on-chip temperatures, but is already widely utilized, and new thermal-specific approaches are necessary. In short, the onus on thermal management is beginning to move from the package designer toward the chip designer. This survey provides an overview of analysis and optimization techniques for thermally aware design. After beginning with a motivation for the problem and trends seen in the semiconductor industry, the survey presents a description of techniques for on-chip thermal analysis. Next, the effects of elevated temperatures on on-chip performance metrics are analyzed. Finally, a set of thermal optimization techniques, for controlling on-chip temperatures and limiting the level to which they degrade circuit performance, are described.ABSTRACT FROM AUTHORCopyright of Foundations &Trends in Electronic Design Automation is the property of Now Publishers and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.
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