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ORCIDIEEE Journal of Solid-State Circuits, Volume 32
Volume 32, Number 1, January 1997
- Kostas Vavelidis, Yannis P. Tsividis, Frank Op't Eynde, Yannis Papananos:
Six-terminal MOSFET's: modeling and applications in highly linear, electronically tunable resistors. 4-12 - Mats Høvin, Alf Olsen, Tor Sverre Lande
, Chris Toumazou:
Delta-sigma modulators using frequency-modulated intermediate values. 13-22 - Steven L. Garverick, Michael L. Nagy, Naresh K. Rao, David K. Hartsfield, Arvind Purushotham:
A capacitive sensing integrated circuit for detection of micromotor critical angles. 23-30 - Hiroyuki Yamada, Masanori Tsunotani, Fumiyasu Kaneyama, Shouhei Seki:
20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems. 31-37 - Ming-Dou Ker, Hun-Hsien Chang, Chung-Yu Wu:
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs. 38-51 - Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina:
A 0.25-μ m CMOS 0.9-V 100-MHz DSP core. 52-61 - Jiren Yuan, Christer Svensson:
New single-clock CMOS latches and flipflops with improved speed and power savings. 62-69 - S. M. Rezaul Hasan, Chakaravarty D. Rajagopal:
Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic. 70-78 - Young-Hee Kim, Jae-Yoon Sim, Hong June Park, Jae-Ik Doh, Kun-Woo Park, Hyun-Woong Chung, Jong-Hoon Oh, Choon-Sik Oh, Seung-Han Ahn:
Analysis and prevention of DRAM latch-up during power-on. 79-85 - Daisaburo Takashima, Yukihito Oowaki:
A novel power-off mode for a battery-backup DRAM. 86-91 - Ho-Jun Song, Jung-Pill Kim, Jae-Jin Lee, Jong-Hoon Oh, Seung-Han Ahn, Inseok Hwang:
A 200 MHz register-based wave-pipelined 64 M synchronous DRAM. 92-99 - Carlo Fiocchi, Guido Torelli, Stefano Ghezzi, Marco Maccarrone:
Program load adaptive voltage generator for flash memories. 100-104 - Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi:
An eight-bit prefetch circuit for high-bandwidth DRAM's. 105-110 - Scott K. Reynolds:
A DC-DC converter for short-channel CMOS technologies. 111-113 - Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su:
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. 114-118 - J. H. Lou, James B. Kuo:
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. 119-121 - Jason P. Hurst, Adit D. Singh:
A differential built-in current sensor design for high-speed IDDQ testing. 122-125 - Steven Galecki:
Multiphase sine-shaper circuit. 126-129 - A. K. Gupta, James W. Haslett, Fred N. Trofimenkoff:
BiCMOS adjustable linear current mirror. 130-134 - Nikos Haralabidis, Dimitris Loukas, Konstantinos Misiakos, Stavros Katsafouros:
A transimpedance CMOS multichannel amplifier with a 50Ω -wide output range buffer for high counting rate applications. 135-138
Volume 32, Number 2, February 1997
- Qiuting Huang:
A MOSFET-only continuous-time bandpass filter. 147-158 - Chung-Yu Wu, Shuo-Yuan Hsiao:
The design of a 3-V 900-MHz CMOS bandpass amplifier. 159-168 - Laszlo Moldovan, Hua Harry Li:
A rail-to-rail, constant gain, buffered op-amp for real time video applications. 169-176 - Philippe Venier, Alessandro Mortara, Xavier Arreguit, Eric A. Vittoz:
An integrated cortical layer for orientation enhancement. 177-186 - Sunetra K. Mendis, Sabrina E. Kemeny, Russell C. Gee, Bedabrata Pain, Craig O. Staller, Quiesup Kim, Eric R. Fossum:
CMOS active pixel image sensors for highly integrated imaging systems. 187-197 - Michael L. Simpson, Charles L. Britton Jr., Alan L. Wintenberg, Glenn R. Young:
An integrated CMOS time interval measurement system with subnanosecond resolution for the WA-98 calorimeter. 198-205 - Zhongde Wang, Graham A. Jullien, William C. Miller, Jinghong Wang, Sami S. Bizzan:
Fast adders using enhanced multiple-output domino logic. 206-214 - Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino:
A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. 215-221 - William Williamson III, Steven B. Enquist, David H. Chow, Howard L. Dunlap, Suresh Subramaniam, Peiming Lei, Gary H. Bernstein, Barry K. Gilbert:
12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates. 222-231 - H. Kato, M. Matsui, K. Sato, H. Shibata, K. Hashimoto, T. Ootani, K. Ochii:
SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober. 232-237 - Kimmo Koli, Kari Halonen:
A fully differential class-AB switched-current integrator for signal processing. 238-244 - Eyad Abou-Allam, Ezz I. El-Masry:
A 200 MHz steered current operational amplifier in 1.2-μ m CMOS technology. 245-249 - Tanchu Shih, Lawrence Der, Stephen H. Lewis, Paul J. Hurst:
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection. 250-253 - Jan Mulder, Marcel van de Gevel, Arthur H. M. van Roermund:
A reduced-area low-power low-voltage single-ended differential pair. 254-257 - Katsuji Kimura:
A bipolar low-voltage quarter-square multiplier with a resistive-input based on the bias offset technique. 258-266 - Richard J. Reay, Klaas B. Klaassen, Calvin S. Nomura:
A resonant switching write driver for magnetic recording. 267-269 - Rohit Mittal, Kimberly C. Bracken, L. Richard Carley, David J. Allstot:
A low-power backward equalizer for DFE read-channel applications. 270-273 - Raquel Pérez-Aloe, J. Francisco Duque-Carrillo, Edgar Sánchez-Sinencio, José M. Valverde, Guido Torelli, Alexander H. Reyes, Franco Maloberti:
Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations. 274-278 - Alireza Moini, Abdesselam Bouzerdoum, Kamran Eshraghian, Andre Yakovleff, Xuan Thong Nguyen, Andrew J. Blanksby, Richard Beare, Derek Abbott, Robert Eugene Bogner:
An insect vision-based motion detection chip. 279-284 - Orly Yadid-Pecht, Bedabrata Pain, Craig O. Staller, Christopher Clark, Eric R. Fossum:
CMOS active pixel sensor star tracker with regional electronic shutter. 285-288 - Seog-Jun Lee, Beomsup Kim, Kwyro Lee:
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. 289-291 - Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. 292 - Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko:
Authors Reply. 293
Volume 32, Number 3, March 1997
- Kwang Young Kim, Naoya Kusayanagi, Asad A. Abidi:
A 10-b, 100-MS/s CMOS A/D converter. 302-311 - Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger:
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. 312-320 - Stephen Au, Bosco H. Leung:
A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops. 321-328 - Ichiro Fujimori, Kazuo Koyama, David Trager, Fred Tam, Lorenzo Longo:
A 5-V single-chip delta-sigma audio A/D converter with 111dB dynamic range. 329-336 - Donald C. Thelen Jr., Dahlon D. Chu:
A low noise readout detector circuit for nanoampere sensor applications. 337-348 - Jean-Baptiste Bégueret, Mohammed Reda Benbrahim, Zhiqun Li, Francis Rodes, Jean Paul Dom:
Converters dedicated to long-term monitoring of strain gauge transducers. 349-356 - John R. Long, Miles A. Copeland:
The modeling, characterization, and design of monolithic inductors for silicon RF IC's. 357-369 - Peter R. Kinget, Michiel S. J. Steyaert:
A 1-GHz CMOS up-conversion mixer. 370-376 - Gilles van Ruymbeke, Christian C. Enz, François Krummenacher, Michel J. Declercq:
A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique. 377-387 - Zhong Yuan Chang, Didier Haspeslagh, Johan Verfaillie:
A highly linear CMOS Gm-C bandpass filter with on-chip frequency tuning. 388-397 - David A. Johns, Daniel Essig:
Integrated circuits for data transmission over twisted-pair channels. 398-406 - Thaddeus J. Gabara, Wilhelm C. Fischer, John Harrington, William W. Troutman:
Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers. 407-418 - Thaddeus J. Gabara, Wilhelm C. Fischer:
Capacitive coupling and quantized feedback applied to conventional CMOS technology. 419-427 - James S. Caravella:
A low voltage SRAM for embedded applications. 428-432 - Renu Mehra, Lisa M. Guerra, Jan M. Rabaey:
A partitioning scheme for optimizing interconnect power. 433-443 - Yasuhiko Hagihara, Shigeto Inui, Fuyuki Okamoto, Masato Nishida, Toshihiko Nakamura, Hachiro Yamada:
Floating-point datapaths with online built-in self speed test. 444-449 - Ravinder S. Kajley, Paul J. Hurst, James E. C. Brown:
A mixed-signal decision-feedback equalizer that uses a look-ahead architecture. 450-459 - Kiyoshi Okamoto, Takuya Jinbo, Toshiyuki Araki, Yasuo Iizuka, Hiromasa Nakajima, Minoru Takahata, Hisashi Inoue, Shun-ichi Kurohmaru, Tomonori Yonezawa, Kunitoshi Aono:
A DSP for DCT-based and wavelet-based video codecs for consumer applications. 460-467 - Jun Rim Choi, Lak Hyun Jang, Seong Wook Jung, Jin Ho Choi:
Structured design of a 288-tap FIR filter by optimized partial product tree compression. 468-476 - Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada:
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. 477-482
Volume 32, Number 4, April 1997
- Klaas-Jan de Langen, Rudy G. H. Eschauzier, Gert J. A. van Dijk, Johan H. Huijsing:
A 1-GHz bipolar class-AB operational amplifier with multipath nested Miller compensation for 76-dB gain. 488-498 - Iuri Mehr, David R. Welland:
A CMOS continuous-time Gm-C filter for PRML read channel applications at 150 Mb/s and beyond. 499-513 - Bang-Sup Song, David C. Soo:
NRZ timing recovery technique for band-limited channels. 514-520 - Mohammad Madihian, Emmanuel Bak, Hiroshi Yoshida, Hiroshi Hirabayashi, Kyotaka Imai, Yasushi Kinoshita, Tohru Yamazaki, Laurent Desclos:
A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks. 521-525 - Chin-Fong Chiu, Chung-Yu Wu:
The design of rotation-invariant pattern recognition using the silicon retina. 526-534 - Antonio J. Montalvo, Ronald S. Gyurcsik, John J. Paulos:
An analog VLSI neural network with on-chip perturbation learning. 535-543 - Tirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama:
Phase-correcting feedback system for class E power amplifier. 544-549 - Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
The delay vernier pattern generation technique. 551-562 - Fang-Shi Lai, Wei Hwang:
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems. 563-573 - Patrik Larsson:
Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance. 574-576 - Wouter A. Serdijn, Martijn Broest, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund:
A low-voltage ultra-low-power translinear integrator for audio filter applications. 577-581 - Howard C. Yang, Lance K. Lee, Ramon S. Co:
A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation. 582-586 - Anna M. Murphy, Shinichi Tsutsumi, Peter Gaussen:
A low-power, low-cost bipolar GPS receiver chip. 587-591 - José Francisco López, Roberto Sarmiento, Kamran Eshraghian, Antonio Núñez:
Noise margin enhancement in GaAs ROM's using current mode logic. 592-597 - Juan M. Casalta, Xavier Aragonès, Antonio Rubio:
Substrate coupling evaluation in BiCMOS technology. 598-603 - Muhammad E. S. Elrabaa, Mohamed I. Elmasry, Duljit S. Malhi:
Low-power BiCMOS circuits for high-speed interchip communication. 604-609 - Wing C. Leung:
A high-performance, low-power complementary coupled BiCMOS circuit. 610-612
Volume 32, Number 5, May 1997
- Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe:
Limitations and challenges of multigigabit DRAM chip design. 624-634 - Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome:
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. 635-641 - Kyu-Chan Lee, Changhyun Kim, Dong-Ryul Ryu, Jai-Hoon Sim, Sang-Bo Lee, Byung-Sik Moon, Keum-Yong Kim, Nam-Jong Kim, Seung-Moon Yoo, Hongil Yoon, Jei-Hwan Yoo, Soo-In Cho:
Low-voltage, high-speed circuit designs for gigabit DRAMs. 642-648 - Hiroshige Hirano, Toshiyuki Honda, Nobuyuki Moriwaki, Tetsuji Nakakuma, Atsuo Inoue, George Nakane, Shigeo Chaya, Tatsumi Sumi:
2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell. 649-654 - Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya:
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. 655-661 - Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi:
A compact on-chip ECC for low cost flash memories. 662-669 - Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto:
A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. 670-680 - Stefanos Sidiropoulos, Mark Horowitz:
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. 681-690 - Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim:
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. 691-700 - William Redman-White:
A high bandwidth constant gm and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems. 701-712 - Bret C. Rothenberg, James E. C. Brown, Paul J. Hurst, Stephen H. Lewis:
A mixed-signal RAM decision-feedback equalizer for disk drives. 713-721 - Paul J. Chang, Ahmadreza Rofougaran, Asad A. Abidi:
A CMOS channel-select filter for a direct-conversion wireless receiver. 722-729 - Behzad Razavi:
A 2-GHz 1.6-mW phase-locked loop. 730-735 - Jan Craninckx, Michiel S. J. Steyaert:
A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors. 736-744 - Derek K. Shaeffer, Thomas H. Lee:
A 1.5-V, 1.5-GHz CMOS low noise amplifier. 745-759 - Seog-Jun Lee, Beomsup Kim, Kwyro Lee:
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application. 760-765 - Tadao Nakagawa, Hideyuki Nosaka:
A direct digital synthesizer with interpolation circuits. 766-770
Volume 32, Number 6, June 1997
- Feng Chen, Bosco Leung:
A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input. 774-782 - Shahriar Rabii, Bruce A. Wooley:
A 1.8-V digital-audio sigma-delta modulator in 0.8-μ m CMOS. 783-796 - Peter J. Black, Teresa H.-Y. Meng:
A 1-Gb/s, four-state, sliding block Viterbi decoder. 797-805 - Peter Nilsson, Mats Torkelson:
A custom digital intermediate frequency filter for the American mobile telephone system. 806-815 - H. Jonathan Chao, Necdet Uzun:
An ATM routing and concentration chip for a scalable multicast ATM switch. 816-828 - Alberto Bilotti, Gerardo Monreal, Ravi Vig:
Monolithic magnetic Hall sensor using dynamic quadrature offset cancellation. 829-836 - Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Jo Saccamango, Louis L.-C. Hsu, Roy C. Flaker, Lawrence F. Wagner, Shao-Fu Sanford Chu, Ghavam G. Shahidi:
SRAM bitline circuits on PD SOI: advantages and concerns. 837-844 - Toru Tanzawa, Tomoharu Tanaka:
A stable programming pulse generator for single power supply flash memories. 845-851 - Chi-Chang Wang, Jiin-Chuan Wu:
Efficiency improvement in charge pump circuits. 852-860 - Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada:
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. 861-869 - John A. McNeill:
Jitter in ring oscillators. 870-879 - Heung-Joon Park, Mani Soma:
Analytical model for switching transitions of submicron CMOS logics. 880-889 - Stephen I. Long, Johnny Qi Zhang:
Low power GaAs current-mode 1.2 Gb/s interchip interconnections. 890-897 - Xiaoyun Hu, Kenneth W. Martin:
A switched-current sample-and-hold circuit. 898-904 - Ion E. Opris, Gregory T. A. Kovacs:
A high-speed median circuit. 905-908 - Jae-Tack Yoo, Kent F. Smith, Ganesh Gopalakrishnan:
A fast parallel squarer based on divide-and-conquer. 909-912 - Chiu-Sing Choy, M. H. Ku, Chi Fat Chan:
A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. 913-917 - P. J. Wright, R. U. Madurawe:
An SRAM cell with nonvolatile memory for programmable logic applications. 918-919 - Ozan Ersan Erdogan:
Comments on "A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter". 920
Volume 32, Number 7, July 1997
- Luca Schillaci, Andrea Baschirotto, Rinaldo Castello:
A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz. 926-932 - Olivier Nys, Robert K. Henderson:
A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging. 933-942 - Vincenzo Peluso, Michiel S. J. Steyaert, Willy Sansen:
A 1.5-V-100-μ WΔ Σ modulator with 12-b dynamic range using the switched-opamp technique. 943-952 - Nicolas Moeneclaey, Andreas Kaiser:
Design techniques for high-resolution current-mode sigma-delta modulators. 953-958