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ORCIDVasant B. Rao
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2010 – 2019
- 2011
[j10]Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez:
Design methodology for the IBM POWER7 microprocessor. IBM J. Res. Dev. 55(3): 9 (2011)
2000 – 2009
- 2002
- [c10]Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang:
Aggressive crunching of extracted RC netlists. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 70-77
1990 – 1999
- 1996
- [j9]John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang:
Design planning for high-performance ASICs. IBM J. Res. Dev. 40(4): 431-452 (1996) - 1995
- [c9]Vasant B. Rao:
Delay Analysis of the Distributed RC Line. DAC 1995: 370-375 - 1994
- [j8]Madhav P. Desai, Vasant B. Rao:
A characterization of the smallest eigenvalue of a graph. J. Graph Theory 18(2): 181-194 (1994) - 1993
- [j7]Madhav P. Desai, Vasant B. Rao:
On the Convergence of Reversible Markov Chains. SIAM J. Matrix Anal. Appl. 14(4): 950-966 (1993) - [j6]K. S. Arun, Vasant B. Rao:
Constructive Heuristics and Lower Bounds for Graph Partitioning Based on a Principal-Components Approximation. SIAM J. Matrix Anal. Appl. 14(4): 991-1015 (1993) - [j5]Sachin S. Sapatnekar
, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang:
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1621-1634 (1993) - 1991
- [j4]Youssef Saab, Vasant B. Rao:
Combinatorial optimization by stochastic evolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 525-535 (1991) - [j3]Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh:
Consistency checking and optimization of macromodels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 957-967 (1991) - [c8]K. S. Arun, Vasant B. Rao:
Rank reduction in graph partitioning. ICASSP 1991: 3297-3300 - [c7]Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya:
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485 - 1990
- [j2]Youssef Saab, Vasant B. Rao:
Fast effective heuristics for the graph bisectioning problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 91-98 (1990) - [c6]Youssef Saab, Vasant B. Rao:
Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. DAC 1990: 26-31
1980 – 1989
- 1989
- [c5]Youssef Saab, Vasant B. Rao:
An Evolution-Based Approach to Partitioning ASIC Systems. DAC 1989: 767-770 - [c4]Youssef Saab, Vasant B. Rao:
A Stochastic Algorithm for Circuit Bi-Partitioning. Great Lakes Computer Science Conference 1989: 313-321 - 1988
- [c3]David C. Yeh, Vasant B. Rao:
Partitioning issues in circuit simulation on multiprocessors. ICCAD 1988: 300-303 - [c2]MahmMahmoud A. Manzoul, Vasant B. Rao:
Multi-Input Fuzzy Inference Engine on a Systolic Array. IEA/AIE (Vol. 2) 1988: 958-964 - 1987
- [j1]Vasant B. Rao, Timothy N. Trick:
Network Partitioning and Ordering for MOS VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(1): 128-144 (1987) - [c1]Shun-Lin Su, Vasant B. Rao, Timothy N. Trick:
HPEX: A Hierarchical Parasitic Circuit Extractor. DAC 1987: 566-569 - 1985
- [b1]Vasant B. Rao:
Switch-Level Timing Simulation of MOS VLSI Circuits. University of Illinois Urbana-Champaign, USA, 1985
Coauthor Index
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