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ORCIDByron Krauter
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2000 – 2009
- 2005
[c18]Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter:
Spatially distributed 3D circuit models. DAC 2005: 153-158- [c17]Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter:
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. DAC 2005: 186-189 - [c16]Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He:
Modeling and Design of Chip-Package Interface. ISQED 2005: 6 - 2003
- [j8]Hui Zheng, Byron Krauter, Lawrence T. Pileggi:
Electrical Modeling of Integrated-Package Power and Ground Distributions. IEEE Des. Test Comput. 20(3): 24-31 (2003) - [c15]Hui Zheng, Byron Krauter, Lawrence T. Pileggi:
On-package decoupling optimization with package macromodels. CICC 2003: 723-726 - [c14]Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter:
Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497 - 2002
- [j7]James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip J. Restle, Brian A. Zoric, Carl J. Anderson:
The circuit and physical design of the POWER4 microprocessor. IBM J. Res. Dev. 46(1): 27-52 (2002) - [j6]Yehea I. Ismail, Byron Krauter:
Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 683-684 (2002) - [j5]Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, Barry J. Rubin, Howard H. Smith:
A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 695-711 (2002) - [c13]Byron Krauter, David Widiger:
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax. DAC 2002: 665-668 - [c12]Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter:
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. DATE 2002: 628-633 - [c11]Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter:
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) 2002: 197-200 - 2001
- [j4]Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie:
A clock distribution network for microprocessors. IEEE J. Solid State Circuits 36(5): 792-799 (2001) - [j3]Alina Deutsch, Paul W. Coteus, Gerard V. Kopcsay, Howard H. Smith, Christopher W. Surovic, Byron Krauter, Daniel C. Edelstein, Phillip J. Restle:
On-chip wiring design challenges for gigahertz operation. Proc. IEEE 89(4): 529-555 (2001) - [j2]Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi:
Equipotential shells for efficient inductance extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 70-79 (2001) - [c10]Howard H. Smith, Aline Deutsch, Sharad Mehrotra, David Widiger, Michael A. Bowen, Allan H. Dansky, Gerard V. Kopcsay, Byron Krauter:
R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip. CICC 2001: 237-240 - 2000
- [c9]Chandramouli V. Kashyap, Byron Krauter:
A realizable driving point model for on-chip interconnect with inductance. DAC 2000: 190-195
1990 – 1999
- 1999
- [c8]Byron Krauter, Sharad Mehrotra, V. Chandramouli:
Including inductive effects in interconnect timing analysis. CICC 1999: 445-452 - 1998
- [c7]Byron Krauter, Sharad Mehrotra:
Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis. DAC 1998: 303-308 - 1997
- [j1]Rohini Gupta, Byron Krauter, Lawrence T. Pileggi:
Transmission line synthesis via constrained multivariable optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 6-19 (1997) - 1996
- [c6]Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi:
A Sparse Image Method for BEM Capacitance Extraction. DAC 1996: 357-362 - [c5]Rohini Gupta, Byron Krauter, Lawrence T. Pileggi:
On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. VLSI Design 1996: 150-155 - 1995
- [c4]Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi:
Transmission Line Synthesis. DAC 1995: 358-363 - [c3]Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi:
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. DAC 1995: 364-369 - [c2]Byron Krauter, Lawrence T. Pileggi:
Generating sparse partial inductance matrices with guaranteed stability. ICCAD 1995: 45-52 - 1993
- [c1]S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, Thomas L. Savarino, Dean P. Neikirk, Lawrence T. Pillage:
An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. ICCAD 1993: 58-65
Coauthor Index
aka: Lawrence T. Pillage
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