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ORCIDN. Ranganathan
Nagarajan Ranganathan
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- affiliation: University of South Florida, Tampa, FL, USA
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2010 – 2019
- 2018
[j85]Santosh Aditham
, Nagarajan Ranganathan:
A System Architecture for the Detection of Insider Attacks in Big Data Systems. IEEE Trans. Dependable Secur. Comput. 15(6): 974-987 (2018)- 2017
- [c158]Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori:
LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems. IPDPS Workshops 2017: 1259-1267 - [i5]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. CoRR abs/1712.02630 (2017) - 2016
- [j84]Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M. Chiarulli, Steven P. Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan, Vijaykrishnan Narayanan:
Enabling New Computation Paradigms with HyperFET - An Emerging Device. IEEE Trans. Multi Scale Comput. Syst. 2(1): 30-48 (2016) - [c157]Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori:
Memory access pattern based insider threat detection in big data systems. IEEE BigData 2016: 3625-3628 - [i4]Santosh Aditham, Nagarajan Ranganathan, Srinivas Katkoori:
Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms. CoRR abs/1611.07392 (2016) - [i3]Santosh Aditham, Nagarajan Ranganathan:
A Novel Control-flow based Intrusion Detection Technique for Big Data Systems. CoRR abs/1611.07649 (2016) - [i2]Santosh Aditham, Nagarajan Ranganathan:
A System Architecture for the Detection of Insider Attacks in Big Data Systems. CoRR abs/1612.01587 (2016) - 2015
- [j83]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Reversible logic based multiplication computing unit using binary tree data structure. J. Supercomput. 71(7): 2668-2693 (2015) - [j82]Matthew A. Morrison, Nagarajan Ranganathan, Jay Ligatti:
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1381-1389 (2015) - [c156]Santosh Aditham, Nagarajan Ranganathan:
A novel framework for mitigating insider attacks in big data systems. IEEE BigData 2015: 1876-1885 - [c155]Tony Casagrande, Nagarajan Ranganathan:
GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. DATE 2015: 677-682 - [c154]Santosh Aditham, Nagarajan Ranganathan:
An energy-aware scheduling heuristic for distributed systems using non-cooperative games. IGSC 2015: 1-6 - 2014
- [j81]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Efficient reversible NOR gates and their mapping in optical computing domain. Microelectron. J. 45(6): 825-834 (2014) - [j80]Matthew Morrison, Nagarajan Ranganathan:
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 975-988 (2014) - [j79]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. Trans. Comput. Sci. 24: 37-55 (2014) - [c153]Yue Wang, Nagarajan Ranganathan:
A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. ISVLSI 2014: 430-435 - [c152]Matthew Morrison, Nagarajan Ranganathan:
Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. VLSID 2014: 470-475 - [c151]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. VLSID 2014: 545-550 - [p1]Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal:
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. Field-Coupled Nanocomputing 2014: 133-172 - [e1]Marina L. Gavrilova, C. J. Kenneth Tan, Himanshu Thapliyal, Nagarajan Ranganathan:
Transactions on Computational Science XXIV - Special Issue on Reversible Computing. Lecture Notes in Computer Science 8911, Springer 2014, ISBN 978-3-662-45710-8 [contents] - 2013
- [j78]Sandip Kundu, Saraju P. Mohanty, Nagarajan Ranganathan:
Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. IET Circuits Devices Syst. 7(5): 221-222 (2013) - [j77]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of efficient reversible logic-based binary and BCD adder circuits. ACM J. Emerg. Technol. Comput. Syst. 9(3): 17:1-17:31 (2013) - [j76]Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo:
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 259-269 (2013) - [j75]Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal:
Design of Testable Reversible Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1201-1209 (2013) - [c150]Matthew Morrison, Nagarajan Ranganathan:
A novel optimization method for reversible logic circuit minimization. ISVLSI 2013: 182-187 - [c149]Matthew Lewandowski, Nagarajan Ranganathan, Matthew Morrison:
Behavioral model of integrated qubit gates for quantum reversible logic design. ISVLSI 2013: 194-199 - [c148]Himanshu Thapliyal, Apeksha Bhatt, Nagarajan Ranganathan:
A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. MWSCAS 2013: 1067-1070 - 2012
- [j74]Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.:
Dynamic clock stretching for variation compensation in VLSI circuit design. ACM J. Emerg. Technol. Comput. Syst. 8(3): 16:1-16:13 (2012) - [c147]Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan:
Run-time power-gating in caches of GPUs for leakage energy savings. DATE 2012: 300-303 - [c146]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE 2012: 721-726 - [c145]Himanshu Thapliyal, Nagarajan Ranganathan:
Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. ISVLSI 2012: 5-6 - [c144]Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI 2012: 207-212 - [c143]Matthew Morrison, Nagarajan Ranganathan:
Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. ISVLSI 2012: 219-224 - [c142]Matthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan:
Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. ISVLSI 2012: 231-236 - [c141]Himanshu Thapliyal, Nagarajan Ranganathan:
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. VLSI Design 2012: 13-15 - 2011
- [j73]Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan:
Redundancy Mining for Soft Error Detection in Multicore Processors. IEEE Trans. Computers 60(8): 1114-1125 (2011) - [j72]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. IEEE Trans. Computers 60(11): 1547-1560 (2011) - [j71]Koustav Bhattacharya, N. Ranganathan:
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 918-923 (2011) - [j70]Upavan Gupta, Nagarajan Ranganathan:
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1723-1726 (2011) - [c140]Yue Wang, N. Ranganathan:
An Instruction-Level Energy Estimation and Optimization Methodology for GPU. CIT 2011: 621-628 - [c139]Himanshu Thapliyal, N. Ranganathan:
A new reversible design of BCD adder. DATE 2011: 1180-1183 - [c138]Matthew Morrison, Nagarajan Ranganathan:
Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. ISVLSI 2011: 126-131 - [i1]Himanshu Thapliyal, Nagarajan Ranganathan:
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits. CoRR abs/1101.4222 (2011) - 2010
- [j69]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. 6(4): 14:1-14:31 (2010) - [j68]Upavan Gupta, Nagarajan Ranganathan:
A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. IEEE Trans. Knowl. Data Eng. 22(4): 465-478 (2010) - [j67]Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt:
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 29-38 (2010) - [j66]Venkataraman Mahalingam, N. Ranganathan:
Timing-Based Placement Considering Uncertainty Due to Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 1007-1011 (2010) - [c137]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. VLSI Design 2010: 235-240
2000 – 2009
- 2009
- [j65]Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. 14(4): 54:1-54:30 (2009) - [j64]Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim:
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 194-206 (2009) - [j63]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
A Framework for Power-Gating Functional Units in Embedded Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1640-1649 (2009) - [c136]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
Compiler-directed leakage reduction in embedded microprocessors. ICCD 2009: 35-40 - [c135]Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan:
A VLSI System Architecture for Optical Flow Computation. ISCAS 2009: 357-360 - [c134]Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori:
Exploring Compiler Optimizations for Enhancing Power Gating. ISCAS 2009: 1004-1007 - [c133]Himanshu Thapliyal, Nagarajan Ranganathan:
Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. ISCAS 2009: 1815-1818 - [c132]Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan:
A Strategy for Soft Error Reduction in Multi Core Designs. ISCAS 2009: 2217-2220 - [c131]Koustav Bhattacharya, Nagarajan Ranganathan:
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED 2009: 388-393 - [c130]Koustav Bhattacharya, Nagarajan Ranganathan:
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. ISVLSI 2009: 91-96 - [c129]Himanshu Thapliyal, Nagarajan Ranganathan:
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. ISVLSI 2009: 229-234 - [c128]Koustav Bhattacharya, Nagarajan Ranganathan:
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design 2009: 453-458 - [c127]Himanshu Thapliyal, Nagarajan Ranganathan:
Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516 - 2008
- [j62]Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow:
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 975-984 (2008) - [c126]N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam:
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI 2008: 171-176 - [c125]Koustav Bhattacharya, Nagarajan Ranganathan:
A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI 2008: 273-278 - [c124]Upavan Gupta, Nagarajan Ranganathan:
A microeconomic approach to multi-objective spatial clustering. ICPR 2008: 1-4 - [c123]Upavan Gupta, Nagarajan Ranganathan:
An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED 2008: 81-86 - [c122]Koustav Bhattacharya, Nagarajan Ranganathan:
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED 2008: 99-104 - [c121]Venkataraman Mahalingam, Nagarajan Ranganathan:
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI 2008: 329-334 - 2007
- [j61]Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan:
VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Comput. Digit. Tech. 1(5): 600-611 (2007) - [j60]K. P. Subbalakshmi, Rajarathnam Chandramouli, Nagarajan Ranganathan:
A Sequential Distinguisher for Covert Channel Identification. Int. J. Netw. Secur. 5(3): 274-282 (2007) - [j59]Upavan Gupta, Nagarajan Ranganathan:
Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers 56(5): 577-589 (2007) - [c120]Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan:
Improving the reliability of on-chip L2 cache using redundancy. ICCD 2007: 224-229 - [c119]Upavan Gupta, Nagarajan Ranganathan:
A microeconomic approach to multi-robot team formation. IROS 2007: 3019-3024 - [c118]Venkataraman Mahalingam, N. Ranganathan:
Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED 2007: 327-332 - [c117]Narender Hanchate, Nagarajan Ranganathan:
Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI 2007: 225-232 - [c116]Narender Hanchate, Nagarajan Ranganathan:
Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI 2007: 245-252 - [c115]Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan:
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design 2007: 215-220 - 2006
- [j58]Narender Hanchate, Nagarajan Ranganathan:
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55(8): 1011-1023 (2006) - [j57]Venkataraman Mahalingam, Nagarajan Ranganathan:
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55(12): 1523-1535 (2006) - [j56]Saraju P. Mohanty, Nagarajan Ranganathan, Karthikeyan Balakrishnan:
A dual voltage-frequency VLSI chip for image watermarking in DCT domain. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 394-398 (2006) - [j55]Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006) - [j54]Narender Hanchate, Nagarajan Ranganathan:
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11(3): 711-739 (2006) - [j53]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006) - [c114]Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III:
A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179 - [c113]Narender Hanchate, Nagarajan Ranganathan:
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED 2006: 92-97 - [c112]Upavan Gupta, N. Ranganathan:
Social Fairness in Multi-Emergency Resource Management. ISTAS 2006: 1-9 - [c111]Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate:
CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI 2006: 329-334 - [c110]Narender Hanchate, Nagarajan Ranganathan:
A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design 2006: 283-290 - [c109]Venkataraman Mahalingam, N. Ranganathan:
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design 2006: 393-398 - [c108]Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh:
An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design 2006: 477-480 - [c107]Aswath Oruganti, Nagarajan Ranganathan:
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design 2006: 766-769 - 2005
- [j52]Saraju P. Mohanty, N. Ranganathan:
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10(2): 330-353 (2005) - [j51]Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
A VLSI architecture for watermarking in a secure still digital camera (S2DC) design. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 808-818 (2005) - [j50]Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
A VLSI architecture for visible watermarking in a secure still digital camera (S2/DC) design (Corrected)*. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 1002-1012 (2005) - [c106]Venkataraman Mahalingam, N. Ranganathan:
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI 2005: 180-185 - [c105]Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan:
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design 2005: 153-158 - [c104]Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591 - 2004
- [j49]Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan:
Stochastic channel-adaptive rate control for wireless video transmission. Pattern Recognit. Lett. 25(7): 793-806 (2004) - [j48]N. Ranganathan:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 1-11 (2004) - [j47]Narender Hanchate, Nagarajan Ranganathan:
LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(2): 196-205 (2004) - [j46]Saraju P. Mohanty, Nagarajan Ranganathan:
A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 562-572 (2004) - [j45]Sanjukta Bhanja, N. Ranganathan:
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1360-1370 (2004) - [c103]Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui:
Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI 2004: 187-192 - [c102]Ashok K. Murugavel, N. Ranganathan:
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design 2004: 195-200 - [c101]Narender Hanchate, Nagarajan Ranganathan:
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design 2004: 228-233 - [c100]Ashok K. Murugavel, N. Ranganathan:
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design 2004: 670- - [c99]Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi:
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design 2004: 745-748 - [c98]Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design 2004: 1063- - 2003
- [j44]Abdel Ejnioui, N. Ranganathan:
Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 71-78 (2003) - [j43]Abdel Ejnioui, N. Ranganathan:
Routing on field-programmable switch matrices. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 283-287 (2003) - [j42]Sanjukta Bhanja, N. Ranganathan:
Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 558-567 (2003) - [j41]Ashok K. Murugavel, N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 921-927 (2003) - [j40]Ashok K. Murugavel, N. Ranganathan:
A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1031-1043 (2003) - [c97]N. Ranganathan, Ashok K. Murugavel:
A low power scheduler using game theory. CODES+ISSS 2003: 126-131 - [c96]