default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 2001: Baltimore, MD, USA
- Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001. IEEE Computer Society 2001, ISBN 0-7803-7169-0
Session 2: IEE 1149 - Beyond DC Testing At Board Test
- Sung Soo Chung, Sanghyeon Baeg:
AC-JTAG: empowering JTAG beyond testing DC nets. 30-37 - Stephen K. Sunter, Ken Filliter, Joe Woo, Pat McHugh:
A general purpose 1149.4 IC with HF analog test capabilities. 38-45 - Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick:
Frequency detection-based boundary-scan testing of AC coupled nets. 46-53
Session 3: Bist Medley
- Peter Wohl, John A. Waicukauski, Thomas W. Williams:
Design of compactors for signature-analyzers in built-in self-test. 54-63 - Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici:
At-speed logic BIST using a frozen clock testing strategy. 64-71 - Nicola Nicolici, Bashir M. Al-Hashimi:
Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. 72-81
Session 4: How Can We Improve Iddq Testing for DSM/VDSM?
- Sagar S. Sabade, D. M. H. Walker:
Improved wafer-level spatial analysis for I_DDQ limit setting. 82-91 - W. Robert Daasch, Kevin Cota, James McNames, Robert Madge:
Neighbor selection for variance reduction in I_DDQ and other parametric data. 92-100 - Bram Kruseman, Rudger van Veen, Kees van Kaam:
The future of delta I_DDQ testing. 101-110
Session 5: Practical Experience With SOC Testing
- Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre:
A building block BIST methodology for SOC designs: a case study. 111-120 - Bart Vermeulen, Steven Oostdijk, Frank Bouwman:
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip. 121-130 - Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay:
CTL the language for describing core-based test. 131-139
Session 6: Some Thorny Problems For Ate Software
- A. T. Sivaram:
Split timing mode (STM)-answer to dual frequency domain testing. 140-147 - Andrew Moran, Jim Teisher, Andrew Gill, Emir Pasalic, John Veneruso:
Automated translation of legacy code for ATE. 148-156 - R. L. Stevenson, M. E. Jarosz, C. V. Verver:
Remote access to engineering test-a case study in providing engineering/diagnostic IC test services to Canadian universities. 157-162
Session 7: Lecture Series: Test and Repair Of Large Embedded Drams
- Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey H. Dreibelbis:
Test and repair of large embedded DRAMs. I. 163-172 - Eric A. Nelson, Jeffrey H. Dreibelbis, Roderick McConnell:
Test and repair of large embedded DRAMs. 2. 173-181 - Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada:
Test cost reduction by at-speed BISR for embedded DRAMs. 182-187
Session 8: DFT Innovations
- Kee Sup Kim, Rathish Jayabharathi, Craig Carstens, Praveen Vishakantaiah, Derek Feltham, Adrian Carbine:
DPDAT: data path direct access testing. 188-195 - Irith Pomeranz, Sudhakar M. Reddy:
A method to enhance the fault coverage obtained by output response comparison of identical circuits. 196-203 - Stephen K. Sunter, Charles McDonald, Givargis Danialy:
Contactless digital testing of IC pin leakage currents. 204-210 - Irith Pomeranz, Sudhakar M. Reddy:
On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. 211-220
Session 9: On-line Test
- Kaijie Wu, Ramesh Karri
:
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. 221-229 - Karl Thaller:
A highly-efficient transparent online memory test. 230-239 - Shu-Yi Yu, Edward J. McCluskey:
On-line testing and recovery in TMR systems for real-time applications. 240-249 - Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari:
GRAAL: a tool for highly dependable SRAMs generation. 250-257
Session 10: Novel Techniques For Fault Diagnosis
- John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. 258-267 - Ruifeng Guo, Srikanth Venkataraman:
A technique for fault diagnosis of defects in scan chains. 268-277 - David B. Lavo, Tracy Larrabee:
Making cause-effect cost effective: low-resolution fault dictionaries. 278-286 - Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski:
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. 287-296
Session 11: Testing Above GigaHertz
- Bernd Laquai, Yi Cai:
Testing gigabit multilane SerDes interfaces with passive jitter injection filters. 297-304 - Amir Attarha, Mehrdad Nourani:
Testing interconnects for noise and skew in gigahertz SoCs. 305-314 - Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A built-in timing parametric measurement unit. 315-322 - Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Testing clock distribution circuits using an analytic signal method. 323-331
Session 12: Test Methods For High-density Modules
- Aranggan Venkataratnam, Kimberly E. Newman:
Rapid prototyping of time-based PDIT for substrate networks [MCM] . 332-339 - Thomas S. Barnett, Adit D. Singh, Victor P. Nelson:
Estimating burn-in fall-out for redundant memory. 340-347 - Mohammad Athar Khalil, Chin-Long Wey:
Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement. 348-357
Session 13: High-quality Test
- Chao-Wen Tseng, Edward J. McCluskey:
Multiple-output propagation transition fault test. 358-366 - Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer:
Switch-level delay test of domino logic circuits. 367-376 - Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. 377-385
Session 14: New IDDX and Energy Test Techniques
- Eric Peterson, Wanli Jiang:
Practical application of energy consumption ratio test. 386-394 - Abhishek Singh, Chintan Patel, Shirong Liao, James F. Plusquellic, Anne E. Gattiker:
Detecting delay faults using power supply transient signal analysis. 395-404 - Hoki Kim, D. M. H. Walker, David Colby:
A practical built-in current sensor for I_DDQ testing. 405-414
Session 15: ATE Hardware: Improving Your Test Results
- Klaus Helmreich:
Test path simulation and characterisation. 415-423 - Sunil K. Jain, Greg P. Chema:
Testing beyond EPA: TDF methodology solutions matrix. 424-432 - G. Dajee, Norman Goldblatt, Ted R. Lundquist, Steven Kasapi, Keneth R. Wilsher:
Practical, non-invasive optical probing for flip-chip devices. 433-442
Session 16: Advanced Microprocessor Test Methodologies
- Ken Tumin, Carmen Vargas, Ross Patterson, Chris Nappi:
Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107TM. 443-450 - Don Douglas Josephson, Steve Poehhnan, Vincent Govan:
Debug methodology for the McKinley processor. 451-460 - Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich:
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. 461-469
Session 17: Lecture Series - Solving Board Test and In-System Problems
- Frans G. M. de Jong, Alex S. Biewenga, D. C. L. (Erik) van Geest, T. F. Waayers:
Testing and programming flash memories on assemblies during high volume production. 470-479 - Stephen Harrison, Peter Collins, Greg Noeninckx, Peter Horwood:
Hierarchical boundary-scan: a Scan Chip-Set solution. 480-486 - Alan Albee:
A practical guide to combining ICT & boundary scan testing. 487-494
Session 18: Mixed-Signal Test Techniques
- Solomon Max:
Ramp testing of ADC transition levels using finite resolution ramps. 495-501 - Udaya Natarajan:
Test challenges for SONET/SDH physical layer OC3 devices and beyond. 502-511 - Mamoru Tamba, Atsushi Shimizu, Hideharu Munakata, Takanori Komuro:
A method to improve SFDR with random interleaved sampling method. 512-520
Session 19: Advanced Techniques for Embedded Core Testing
- Ozgur Sinanoglu, Alex Orailoglu:
Space and time compaction schemes for embedded cores. 521-529 - Rainer Dorsch, Hans-Joachim Wunderlich:
Tailoring ATPG for embedded testing. 530-537 - Frank F. Hsu, Kenneth M. Butler, Janak H. Patel:
A case study on the implementation of the Illinois Scan Architecture. 538-547
Session 20: Test Generation for Crosstalk Faults
- Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer:
Crosstalk test generation on pseudo industrial circuits: a case study. 548-557 - Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng:
Delay testing considering crosstalk-induced effects. 558-567 - Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu:
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. 568-577
Session 21: Microprocessor Testing
- Don Douglas Josephson, Steve Poehlman, Vincent Govan, Clint Mumford:
Test methodology for the McKinley processor. 578-585 - Mary P. Kusko, Bryan J. Robbins, Timothy J. Koprowski, William V. Huott:
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor. 586-592 - Gilbert Vandling:
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo. 593-599
Session 22: Standards and Techniques - Board Test Development
- Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei:
Towards a unified test process: from UML to end-of-line functional test. 600-608 - Robert Tappe, Dietmar Ehrhardt:
Dynamic tests in complex systems [automotive electronics]. 609-614 - William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo:
Unsafe board states during PC-based boundary-scan testing. 615-623
Session 23: Delay Test
- Jeff Rearick:
Too much delay fault coverage is a bad thing. 624-633 - Manish Sharma, Janak H. Patel:
Testing of critical paths for delay faults. 634-641 - Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas:
Exact path delay grading with fundamental BDD operations. 642-651
Session 24: Ideas for Low-Power Scan Operation
- Lei Xu, Yihe Sun, Hongyi Chen:
Scan array solution for testing power and testing time. 652-659 - Tsung-Chu Huang, Kuen-Jong Lee:
A token scan architecture for low power testing. 660-669 - Jayashree Saxena, Kenneth M. Butler, Lee Whetsel:
An analysis of power reduction techniques in scan testing. 670-677
Session 25: Uncovering and Understanding Why Circuits Fail
- Nandini Sridhar, Michael S. Hsiao:
On efficient error diagnosis of digital circuits. 678-687 - Venkatram Krishnaswamy, A. B. Ma, Praveen Vishakantaiah:
A study of bridging defect probabilities on a Pentium (TM) 4 CPU. 688-695 - Zoran Stanojevic, D. M. H. Walker:
FedEx - a fast bridging fault extractor. 696-703
Session 26: ATE HW: Conquering Those Stubborn Test Problems
- Chintan Patel, Fidel Muradali, James F. Plusquellic:
Power supply transient signal integration circuit. 704-712 - Jamie Cullen:
Scan test sequencing hardware for structural test. 713-720
Session 27: Advances in Scan Testing
- Rohit Kapur, Thomas W. Williams:
Tester retargetable patterns. 721-727 - Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy:
On RTL scan design. 728-737 - Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
Enhanced reduced pin-count test for full-scan design. 738-747 - Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko:
OPMISR: the foundation for compressed ATPG vectors. 748-757
Session 28: Memory Testing
- Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults. 758-767 - Jörg E. Vollrath, Randall Rooney:
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. 768-775 - Harold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers:
Bitline contacts in high density SRAMs: design for testability and stressability. 776-782 - Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter:
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. 783-792
Session 29: Increasing Design Validation Coverage
- Gilly Nativ, Steven Mittermaier, Shmuel Ur, Avi Ziv:
Cost evaluation of coverage directed test generation for the IBM mainframe. 793-802 - Zeljko Zilic, Katarzyna Radecka:
: Identifying redundant gate replacements in verification by error modeling. 803-812 - Qiushuang Zhang, Ian G. Harris:
A validation fault model for timing-induced functional errors. 813-820 - Alessandro Fin, Franco Fummi, Graziano Pravadelli:
AMLETO: a multi-language environment for functional test generation. 821-829
Session 30: PLL AND Jitter Testing
- Seongwon Kim, Mani Soma:
Test evaluation and data on defect-oriented BIST architecture for high-speed PLL. 830-837 - Sasikumar Cherubal, Abhijit Chatterjee:
A high-resolution jitter measurement technique using ADC sampling. 838-847 - Masashi Shimanouchi:
An approach to consistent jitter modeling for various jitter aspects and measurement methods. 848-857 - Antonio H. Chan, Gordon W. Roberts:
A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line. 858-867
Session 31: New Ideas for BIST TPG
- Seongrnoon Wang:
Low hardware overhead scan based 3-weight weighted random BIST. 868-877 - Hong-Sik Kim, Jin-kyue Lee, Sungho Kang:
A new multiple weight set calculation algorithm. 878-884 - C. V. Krishna, Abhijit Jas, Nur A. Touba:
Test vector encoding using partial LFSR reseeding. 885-893 - Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:
Two-dimensional test data compression for scan-based deterministic BIST. 894-902
Session 32: Test Automation; Improbing IC Test Efficiency
- Mark Malinoski, Burnell G. West:
Rapid-response temperature control provides new defect screening opportunities. 903-907 - Scott Benner, Oluseyi Boroffice:
Optimal production test times through adaptive test programming. 908-915 - Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir:
A new methodology for improved tester utilization. 916-923
Session 33: FPGA Testing
- Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan. 924-931 - Ian G. Harris, Premachandran R. Menon, Russell Tessier:
BIST-based delay path testing in FPGA architectures. 932-938 - Cecilia Metra, Andrea Pagano, Bruno Riccò:
On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems. 939-947
Session 34: RF Testing
- John Ferrario, Randy Wolf, Hanyi Ding:
Moving from mixed signal to RF test hardware development. 948-956 - Hui S. Nam, Bernard Cuddy, Dieter Luecking:
A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipments. 957-964 - Christian Olgaard, Sule Ozev, Alex Orailoglu:
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. 965-974
Session 35: Embedded Memories Test and Repair
- Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM built in self test and methodology for test insertion. 975-984 - Yuejian Wu, Liviu Calin:
Shadow write and read for at-speed BIST of TDM SRAMs. 985-994 - Volker Schöber, Steffen Paul, Olivier Picot:
Memory built-in self-repair using redundant words. 995-1001
Session 36: Lecture Series - Logic BIST Case Studies
- Xinli Gu, Sung Soo Chung, Frank Tsang, Jan Arild Tofte, Hamid Rahmanian:
An effort-minimized logic BIST implementation method. 1002-1010 - Snezana Dikic, Lars-Johan Fritz, Dario Dell'Aquia:
BIST and fault insertion re-use in telecom systems. 1011-1016 - John Braden, Qing Lin, Brian Smith:
Use of BIST in Sun FireTM servers. 1017-1022
Session 37: Advanced Methods in Embedded Core Test
- Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Test wrapper and test access mechanism co-optimization for system-on-chip. 1023-1032 - Chauchin Su, Wenliang Tseng:
Configuration free SoC interconnect BIST methodology. 1033-1038
Session 38: How Could We Model and Test VDSM Defects
- Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short. 1039-1048 - Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey:
Testing for resistive opens and stuck opens. 1049-1058 - Yasuo Sato, Masaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto:
An evaluation of defect-oriented test: WELL-controlled low voltage test. 1059-1067
Session 39: Practical Test Generation Techniques
- Srivaths Ravi, Niraj K. Jha:
Fast test generation for circuits with RTL and gate-level views. 1068-1077 - Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Combinational test generation for various classes of acyclic sequential circuits. 1078-1087 - Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs. 1088-1097
Session 40: Delving into Factors Affecting Manufacturing Cost
- Erik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff:
Tackling test trade-offs from design, manufacturing to market using economic modeling. 1098-1107 - Thiagarajan Trichy, Peter Sandborn, Ravi Raghavan, Shubhada Sahasrabudhe:
A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly. 1108-1117