The front end of line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate.[1] FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers.[2]
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Steps
editFor the CMOS process, FEOL contains all fabrication steps needed to form isolated CMOS elements:[3][4]
- Selecting the type of wafer to be used; Chemical-mechanical planarization (CMP) and cleaning of the wafer.
- Shallow trench isolation (STI) (or LOCOS in early processes with feature size > 0.25
μ m); - Well formation;
- Gate module formation;
- Source and drain module formation.
Finally, the surface is treated to prepare the contacts for the subsequent metallization. This concludes the FEOL process, that is, all devices have been built.[4]
Following these steps, the devices must be connected electrically as per the nets to build the electrical circuit. This is done in the back end of line (BEOL). BEOL is thus the second portion of IC fabrication where the individual devices are connected.[4]
See also
editReferences
edit- ^ Karen A. Reinhardt and Werner Kern (2008). Handbook of Silicon Wafer Cleaning Technology (2nd ed.). William Andrew. p. 202. ISBN 978-0-8155-1554-8.
- ^ "FEOL (Front End of Line: substrate process, the first half of wafer processing) 1. Isolation | USJC：United Semiconductor Japan Co., Ltd". USJC：United Semiconductor Japan Co., Ltd. |
三重 県 桑名 市 の300mm半導体 ウェーハ工場 を製造 拠点 にしたファウンドリ専業 メーカーです。超 低 消費 電力 、不揮発 メモリなど先進 テクノロジーを世界中 のお客様 に提供 しています。 (in Japanese). 2019-02-22. Retrieved 2022-09-27. - ^ Ramsundar, Bharath. "A Deep Dive into Chip Manufacturing: Front End of Line (FEOL) Basics". deepforest.substack.com. Retrieved 2022-09-27.
- ^ a b c J. Lienig, J. Scheible (2020). "Chap. 2.9.3: FEOL: Creating Devices". Fundamentals of Layout Design for Electronic Circuits. Springer. pp. 78–82. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
Further reading
edit- "CMOS: Circuit Design, Layout, and Simulation" Wiley-IEEE, 2010. ISBN 978-0-470-88132-3. pages 177-178 (Chapter 7.2 CMOS Process Integration); pages 180-199 (7.2.1 Frontend-of-the-line integration)
- "Fundamentals of Layout Design for Electronic Circuits", by Lienig, Scheible, Springer, doi:10.1007/978-3-030-39284-0ISBN 978-3-030-39284-0, 2020. Chapter 2: Technology Know-How: From Silicon to Devices, pages 78-82 (2.9.3 FEOL: Creating Devices)