In computer central processing units, micro-operations (also known as micro-ops or
![](https://upload.wikimedia.org/wikipedia/commons/thumb/9/97/Micro-operations.svg/460px-Micro-operations.svg.png)
Usually, micro-operations perform basic operations on data stored in one or more registers, including transferring data between registers or between registers and external buses of the central processing unit (CPU), and performing arithmetic or logical operations on registers. In a typical fetch-decode-execute cycle, each step of a macro-instruction is decomposed during its execution so the CPU determines and steps through a series of micro-operations. The execution of micro-operations is performed under control of the CPU's control unit, which decides on their execution while performing various optimizations such as reordering, fusion and caching.[1]
Optimizations
editVarious forms of
This buffering means that the fetch and decode stages can be more detached from the execution units than is feasible in a more traditional microcoded (or hard-wired) design. As this allows a degree of freedom regarding execution order, it makes some extraction of instruction-level parallelism out of a normal single-threaded program possible (provided that dependencies are checked, etc.). It opens up for more analysis and therefore also for reordering of code sequences in order to dynamically optimize mapping and scheduling of
Execution optimization has gone even further; processors not only translate many machine instructions into a series of
Another way to try to improve performance is to cache the decoded micro-operations in a micro-operation cache, so that if the same macroinstruction is executed again, the processor can directly access the decoded micro-operations from the cache, instead of decoding them again. The execution trace cache found in Intel NetBurst microarchitecture (Pentium 4) is a widespread example of this technique.[5] The size of this cache may be stated in terms of how many thousands (or strictly multiple of 1024) of micro-operations it can store: K
References
edit- ^ a b "Computer Organization and Architecture, Chapter 15. Control Unit Operation" (PDF). umcs.maine.edu. 2010-03-16. Retrieved 2014-12-29.
- ^ FM1600B Microcircuit Computer Ferranti Digital Systems (PDF). Bracknell, Berkshire, UK: Ferranti Limited, Digital Systems Department. October 1968 [September 1968]. List DSD 68/6. Archived (PDF) from the original on 2020-05-19. Retrieved 2020-05-19.
- ^ a b c Agner Fog (2014-02-19). "The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers" (PDF). agner.org. Retrieved 2014-03-21.
- ^ a b c Michael E. Thomadakis (2011-03-17). "The Architecture of the Nehalem Processor and Nehalem-EP SMP Platforms" (PDF). Texas A&M University. Archived from the original (PDF) on 2014-08-11. Retrieved 2014-03-21.
- ^ "Intel Pentium 4 1.4GHz & 1.5GHz". AnandTech. 2000-11-20. Retrieved 2013-10-06.
- ^ Baruch Solomon; Avi Mendelson; Doron Orenstein; Yoav Almog; Ronny Ronen (August 2001). "Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA" (PDF). ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581). Intel. pp. 4–9. doi:10.1109/LPE.2001.945363. ISBN 1-58113-371-5. S2CID 10934861. Retrieved 2014-03-21.