Parallel Thread Execution
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Parallel Thread Execution (PTX or NVPTX[1]) is a low-level parallel thread execution virtual machine and instruction set architecture used in Nvidia's Compute Unified Device Architecture (CUDA) programming environment. The Nvidia CUDA Compiler (NVCC) translates code written in CUDA, a C++-like language, into PTX instructions (an assembly language represented as American Standard Code for Information Interchange (ASCII) text), and the graphics driver contains a compiler which translates PTX instructions into executable binary code,[2] which can run on the processing cores of Nvidia graphics processing units (GPUs). The GNU Compiler Collection also has basic ability to generate PTX in the context of OpenMP offloading.[3] Inline PTX assembly can be used in CUDA.[4]
Registers
[edit]PTX uses an arbitrarily large processor register set; the output from the compiler is almost pure static single-assignment form, with consecutive lines generally referring to consecutive registers. Programs start with declarations of the form
.reg .u32 %r<335>; // declare 335 registers %r0, %r1, ..., %r334 of type unsigned 32-bit integer
It is a three-argument assembly language, and almost all instructions explicitly list the data type (in sign and width) on which they operate. Register names are preceded with a % character and constants are literal, e.g.:
shr.u64 %rd14, %rd12, 32; // shift right an unsigned 64-bit integer from %rd12 by 32 positions, result in %rd14
cvt.u64.u32 %rd142, %r112; // convert an unsigned 32-bit integer to 64-bit
There are predicate registers, but compiled code in shader model 1.0 uses these only in conjunction with branch commands; the conditional branch is
@%p14 bra $label; // branch to $label
The setp.cc.type instruction sets a predicate register to the result of comparing two registers of appropriate type, there is also a set instruction, where set.le.u32.u64 %r101, %rd12, %rd28 sets the 32-bit register %r101 to 0xffffffff if the 64-bit register %rd12 is less than or equal to the 64-bit register %rd28. Otherwise %r101 is set to 0x00000000.
There are a few predefined identifiers that denote pseudoregisters. Among others, %tid, %ntid, %ctaid, and %nctaid contain, respectively, thread indices, block dimensions, block indices, and grid dimensions.[5]
State spaces
[edit]Load (ld) and store (st) commands refer to one of several distinct state spaces (memory banks), e.g. ld.param.
There are eight state spaces:[5]
.reg- registers
.sreg- special, read-only, platform-specific registers
.const- shared, read-only memory
.global- global memory, shared by all threads
.local- local memory, private to each thread
.param- parameters passed to the kernel
.shared- memory shared between threads in a block
.tex- global texture memory (deprecated)
Shared memory is declared in the PTX file via lines at the start of the form:
.shared .align 8 .b8 pbatch_cache[15744]; // define 15,744 bytes, aligned to an 8-byte boundary
Writing kernels in PTX requires explicitly registering PTX modules via the CUDA Driver API, typically more cumbersome than using the CUDA Runtime API and Nvidia's CUDA compiler, nvcc. The GPU Ocelot project provided an API to register PTX modules alongside CUDA Runtime API kernel invocations, though the GPU Ocelot is no longer actively maintained.[6]
See also
[edit]- Standard Portable Intermediate Representation (SPIR)
- CUDA binary (cubin) – a type of fat binary
References
[edit]- ^ "User Guide for NVPTX Back-end – LLVM 7 documentation". llvm.org.
- ^ "CUDA Binary Utilities". docs.nvidia.com. Retrieved 2019-10-19.
- ^ "nvptx". GCC Wiki.
- ^ "Inline PTX Assembly in CUDA". docs.nvidia.com. Retrieved 2019-11-03.
- ^ a b "PTX ISA Version 2.3" (PDF).
- ^ "GPUOCelot: A dynamic compilation framework for PTX". github.com. 7 November 2022.