(Translated by https://www.hiragana.jp/)
HDL Util · GitHub
Skip to content
@hdl-util

HDL Util

Various MIT/Apache 2.0 licensed IP for FPGAs

Pinned Loading

  1. hdmi hdmi Public

    Send video/audio over HDMI on an FPGA

    SystemVerilog 1.1k 112

  2. sdram-controller sdram-controller Public

    Generic FPGA SDRAM controller, originally made for AS4C4M16SA

    Verilog 78 11

  3. i2c i2c Public

    Fully featured implementation of Inter-IC (I2C) bus master for FPGAs

    SystemVerilog 21 2

Repositories

Showing 10 of 15 repositories
  • hdmi Public

    Send video/audio over HDMI on an FPGA

    hdl-util/hdmi’s past year of commit activity
    SystemVerilog 1,087 112 11 (1 issue needs help) 2 Updated Feb 3, 2024
  • hdmi-demo Public

    Demo of hdmi on at 720p with VGA-compatible text mode and sound

    hdl-util/hdmi-demo’s past year of commit activity
    Verilog 24 8 3 0 Updated Jan 27, 2023
  • mipi-demo Public

    MIPI CSI-2 + MIPI CCS Demo

    hdl-util/mipi-demo’s past year of commit activity
    Verilog 65 21 3 0 Updated May 27, 2021
  • unipolar-rz Public
    hdl-util/unipolar-rz’s past year of commit activity
    SystemVerilog 1 0 0 0 Updated Mar 7, 2021
  • sdram-controller Public

    Generic FPGA SDRAM controller, originally made for AS4C4M16SA

    hdl-util/sdram-controller’s past year of commit activity
    Verilog 78 11 0 0 Updated Sep 7, 2020
  • image-processing Public

    SystemVerilog code for image processing tasks like demosaicing

    hdl-util/image-processing’s past year of commit activity
    SystemVerilog 10 3 0 0 Updated Jun 28, 2020
  • rand Public

    Random number generators such as LFSRs, LHCAs

    hdl-util/rand’s past year of commit activity
    SystemVerilog 4 2 0 0 Updated Jun 27, 2020
  • clock-domain-crossing Public

    Utilities for clock-domain crossing with an FPGA

    hdl-util/clock-domain-crossing’s past year of commit activity
    SystemVerilog 7 2 0 0 Updated Jun 27, 2020
  • gray-code Public

    Generate a gray code of arbitrary width in SystemVerilog

    hdl-util/gray-code’s past year of commit activity
    SystemVerilog 3 1 1 (1 issue needs help) 0 Updated Jun 27, 2020
  • mipi-csi-2 Public

    Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA

    hdl-util/mipi-csi-2’s past year of commit activity
    SystemVerilog 64 16 0 0 Updated Jun 22, 2020
View all repositories

Top languages

Loading…

Most used topics

Loading…