AMF-Placer 2.0 is an open-source comprehensive timing-driven Analytical Mixed-size FPGA placer. It supports mixed-size placement of heterogeneous resources (e.g., LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM) on FPGA. To speed up the convergence and improve the timing quality of the placement, standing upon the shoulders of AMF-Placer 1.0, AMF-Placer 2.0 is equipped with a series of new techniques for timing optimization, including an effective regression-based timing model, placement-blockage-aware anchor insertion, WNS-aware timing-driven quadratic placement, and sector-guided detailed placement. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that critical path delays realized by AMF-Placer 2.0 are averagely 2.2% and 0.59% higher than those achieved by commercial tool Xilinx Vivavo 2020.2 and 2021.2 respectively. Meanwhile, the average runtime of placement procedure of AMF-Placer 2.0 is 14% and 8.5% higher than Xilinx Vivavo 2020.2 and 2021.2 respectively. Although limited by the absence of the exact timing model of the device, the information of design hierarchy and accurate routing feedback, AMF-Placer 2.0 is the first open-source FPGA placer which can handle the timing-driven mixed-size placement of practical complex designs with various FPGA resources and achieves the comparable quality to the latest commercial tools. Detailed Docygen-based documentation (e.g, introduction, usage, implementation and experimental results) can be accessed here.

AMF-Placer 2.0 is the extension of AMF-Placer 1.0. AMF-Placer 1.0 is a wirelength-driven mixed-size FPGA placer equipped with a series of new techniques for wirelength optimization, cell spreading, packing, and legalization. Experimental results indicate that AMF-Placer can improve HPWL by 20.4%-89.3% and reduce runtime by 8.0%-84.2%, compared to the baseline. Furthermore, utilizing the parallelism of the proposed algorithms, with 8 threads, the placement procedure can be accelerated by 2.41x on average.

This project is developed by Reconfiguration Computing Systems Lab, Hong Kong University of Science and Technology (HKUST). Tingyuan Liang (tliang@connect.ust.hk), Gengjie Chen (chen_gengjie.hotmail.com), Jieru Zhao (zhao-jieru.sjtu.edu.cn), Sharad Sinha (sharad@iitgoa.ac.in) and Wei Zhang (eeweiz@ust.hk) are the major contributors of this project.

In this repo, we provide the initial implementation of AMF-Placer 2.0, supporting comprehensive timing-driven placement with critical path delay and runtime which are downgraded by ~5%. If you want to reproduce the experimental results in the paper of AMF-Placer 2.0 for academic evaluation or commercial usage, you are required to contact the authors Tingyuan Liang (tliang@connect.ust.hk) and Wei ZHANG (eeweiz@ust.hk) with your offcial instituation email and we will response in 72 hours. Generally, for non-commercial usage of this open-source project, users should comply the Apache License attached in the root directory and for commercial usage of this open-source project, users must contact project supervisor (Wei ZHANG, eeweiz@ust.hk) for authorization.

If our works are involved in your works, please cite our papers:

[1] AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA(pre-print)

@INPROCEEDINGS{AMFPlacer,  
   title={AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA},
   author={Liang, Tingyuan and Chen, Gengjie and Zhao, Jieru and Sinha, Sharad and Zhang, Wei},  
   booktitle={2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},   
   year={2021},  volume={},  number={},  pages={1-6},
}

[2] AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA(pre-print)

@article{liang2022amf,
  title={AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA},
  author={Liang, Tingyuan and Chen, Gengjie and Zhao, Jieru and Sinha, Sharad and Zhang, Wei},
  journal={arXiv preprint arXiv:2210.08682},
  year={2022}
}

1. Just reinvent the wheel for fun, try to build a complete flow and reproduce/improve some state-of-art techniques in the latest papers.
2. Resolve some existing constraints in some previous works and consider more practical situations, like FPGA mixed-size placement with a series of optimization from the perspectives of timing, clocking, routability-aware and parallelism.
3. A beginner-friendly placement framework with clear hierarchy and detailed Doxygen-based documentation. We hope that it can lower the overhead for people who are also interested in this research area.
4. Currently, this framework is under development and it is still far from our goals and the practical demands, but we are happy to share our progress in this GitHub repository. If you have any questions/problems/suggestions, please contact feel free to contact us (Tingyuan LIANG, tliang@connect.ust.hk)

1. supports placeemnt with a large number of mixed-size macros with shape constraints in practical FPGA applications.
2. wirelength-driven, routability-aware, packing-aware, clock-aware, region-aware.
3. initially timing-driven with basic embedded static timing analysis, WNS-aware global placement, efficient detailed placement
4. a set of optional optimization techniques to improve mixed-size FPGA placement QoR
5. parallelizes the implementation of each stage of placement based on multi-threading
6. modularized function implementation for easier further development
7. flexible and extensible JSON-based placement configuration
8. supports placement check-point importing/exporting
9. a set of pre-implementation benchmarks from latest practical FPGA applications
10. provides a set of Tcl scripts which extracts design netlist from Vivado and exports post-placement information to Vivado

Below is a hiearchy tree of this project. As for the details, please refer to the class information and collaboration diagram in the Doxygen documentation and trace the implementation, e.g., AMFPlacer, GlobalPlacer, and PlacementInfo.

├── benchmarks  // benchmark information
│   ├── analysisScripts  // experimental result analysis Python scripts
│   ├── testConfig       // some test settings of placer
│   ├── VCU108           // information of design and device for VCU108
│   │   ├── compatibleTable    // mapping information between design and device
│   │   ├── design             // design information
│   │   └── device             // device information
│   └── vivadoScripts    // some Vivado Tcl scripts to extract design/device information
├── build                // potential target directory for built output
├── doc                  // documentation-related materials
└── src                  // source code of the project
    ├── app              // application (e.g., AMFPlacer)
    │   └── AMFPlacer    // A High-Performance Analytical Mixed-size Placer for FPGA
    └── lib              // libraries for application implementation
        ├── 3rdParty     // third-party libraries
        ├── HiFPlacer    // our placement function modules
        │   ├── designInfo
        │   ├── deviceInfo
        │   ├── placement
        │   │   ├── globalPlacement
        │   │   ├── legalization
        │   │   ├── packing
        │   │   ├── placementInfo
        │   │   └── placementTiming
        │   └── problemSolvers
        └── utils        // some minor utility functions

1. eigen 3.3.8 (source code included)
2. PaToH (library included)
3. osqp (source code included)
4. Qt5 (for GUI, you can install it on Ubuntu by: sudo apt-get install qt5-default )
5. MKL (optional)
6. opengl, freeglut, glew (optional)

1. clock tree synthesis
2. ckock-related optimization

This project is under active development and far from perfect. We do want to make the placer useful for people in the community. Therefore,

• If you have any question/problem, please feel free to create an issue in the GitHub Issue or email us (Tingyuan LIANG, tliang@connect.ust.hk)
• We sincerely welcome code contribution to this project or suggestion in any approach!

(last updated Oct 23, 2022)