A first attempt to implement a 6502 in verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 81 Commits
circ		circ
.gitignore		.gitignore
6502_functional_test.bin		6502_functional_test.bin
6502_functional_test.lst		6502_functional_test.lst
MEMORY.v		MEMORY.v
Makefile		Makefile
README.md		README.md
alu4.v		alu4.v
alu8.v		alu8.v
cpu.cpp		cpu.cpp
cpu.v		cpu.v
go.sh		go.sh
pg.v		pg.v
test.sh		test.sh
test_results.txt		test_results.txt
top.pcf		top.pcf
top.v		top.v

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