32-bit Superscalar RISC-V CPU
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Updated
Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
Over-engineered SDR development board
HDU Computer Organization Course Design Beginner Guide -
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
My experiments with Nexys4 DDR Artix-7 FPGA Board
A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.
Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
A tetris-game on screen using verilog.
Alchitry Au FPGA Board Example Project
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.
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