ghdl

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Here are 76 public repositories matching this topic...

ghdl / ghdl

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VHDL 2008/93/87 simulator

simulator compiler hardware llvm vhdl gcc ghdl hacktoberfest testbench

Updated Nov 14, 2024
VHDL

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Nov 14, 2024
Python

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

jakubcabal / spi-fpga

Sponsor

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SPI master and SPI slave for FPGA written in VHDL

fpga controller vhdl accelerometer spi ghdl spi-master spi-slave cyc1000 spi-loopback spi-controller

Updated Apr 24, 2021
VHDL

jakubcabal / uart-for-fpga

Sponsor

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Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Aug 7, 2021
VHDL

PyFPGA / pyfpga

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A Python package to use FPGA development tools programmatically.

Updated Nov 12, 2024
Python

Paebbels / JSON-for-VHDL

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A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Sep 5, 2022
VHDL

stnolting / neorv32-setups

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📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga vhdl intel verilog xilinx lattice soc ghdl yosys risc-v neorv32

Updated Nov 11, 2024
VHDL

tmeissner / psl_with_ghdl

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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Jan 30, 2023
VHDL

stnolting / neorv32-verilog

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♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Nov 11, 2024
Verilog

tmeissner / formal_hw_verification

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Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Mar 7, 2024
VHDL

tmeissner / cryptocores

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cryptography ip-cores in vhdl / verilog

cryptography fpga vhdl verilog testbenches ghdl

Updated Feb 20, 2021
VHDL

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Jun 6, 2024
Shell

dbhi / vboard

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Virtual development board for HDL design

vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Updated Mar 31, 2023
VHDL

mnemocron / my-discrete-fpga

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My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

fpga vhdl ghdl fpga-soc 7400 breadboard-computer

Updated Apr 20, 2024
VHDL

tmeissner / libvhdl

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Library of reusable VHDL components

coverage fpga vhdl verification assertions testbenches ghdl formal-verification osvvm psl

Updated Mar 7, 2024
VHDL

stnolting / neorv32-riscof

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✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

processor vhdl verification riscv isa ghdl risc-v neorv32 riscof sail-riscv

Updated Nov 11, 2024
Python

wyvernSemi / mem_model

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High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Oct 22, 2024
VHDL

tmeissner / gatemate_experiments

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Experiments with Cologne Chip's GateMate FPGA architecture

fpga vhdl verilog ghdl yosys gatemate

Updated Nov 16, 2023
VHDL

SalvatoreBarone / CNN-VHDL

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A library of VHDL components for Neural Networks

vhdl artificial-intelligence approximation artificial-neural-networks convolutional-neural-networks ghdl xilinx-fpga lenet-5 approximate-computing approximate-algorithms virtex

Updated Sep 23, 2021
C++

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ghdl

Here are 76 public repositories matching this topic...

ghdl / ghdl

olofk / edalize

suoto / hdl_checker

jakubcabal / spi-fpga

jakubcabal / uart-for-fpga

PyFPGA / pyfpga

Paebbels / JSON-for-VHDL

stnolting / neorv32-setups

tmeissner / psl_with_ghdl

stnolting / neorv32-verilog

tmeissner / formal_hw_verification

tmeissner / cryptocores

ghdl / docker

dbhi / vboard

mnemocron / my-discrete-fpga

tmeissner / libvhdl

stnolting / neorv32-riscof

wyvernSemi / mem_model

tmeissner / gatemate_experiments

SalvatoreBarone / CNN-VHDL

Improve this page

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