RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 29 public repositories matching this topic...
SonicBOOM: The Berkeley Out-of-Order Machine
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Aug 14, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Sep 7, 2024 - Scala
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Jan 23, 2020 - Scala
Quasar 2.0: Chisel equivalent of SweRV-EL2
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Apr 13, 2021 - Scala
BOOM's Simulation Accelerator.
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Dec 16, 2021 - Scala