VUnit is a unit testing framework for VHDL/SystemVerilog
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Updated
Aug 21, 2024 - VHDL
VUnit is a unit testing framework for VHDL/SystemVerilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
HDL support for VS Code
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
High throughput JPEG decoder in Verilog for FPGA
Image Processing Toolbox in Verilog using Basys3 FPGA
A complete open-source design-for-testing (DFT) Solution
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
5-stage pipelined 32-bit MIPS microprocessor in Verilog
A simple implementation of a UART modem in Verilog.
2017级北
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
This is a tutorial on standard digital design flow
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
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