LiteX と Migen の勉強 をしてみる(第 1回 )
Slowly start learning LiteX and Migen.
Slowly start learning LiteX and Migen.
Running code on SPI ROM of TinyFPGA BX with VexRiscv (small) Briey SoC, or XiP (execute-in-place) in short.
Added an AXI4 bus master (DMA) to Briey, RISC-V SoC written by SpinalHDL.
Running VexRiscv SoC with AXI4 crossbar on TinyFPGA BX.
Added SPI Peripheral functionality to Murax (free RISC-V SoC).
Investigating bus transactions between VexRiscv core and memory. FPGA
Added a PWM output control to VexRiscv (RISC-V) Murax Soc.
Just ran softcore processor VexRiscv (RISC-V of course) on TinyFPGA-BX without XIP functionality.
Reading SpinalHDL original UART code to get better insight. いままで、SpinalHDL で
By adding APB3 and a state machine to my UART, convert character code on TinyFPGA BX.