数かず据すえ通路つうろ

数かず据すえ通路つうろ是ぜ执行单元的てき集合しゅうごう，例れい如执行ぎょう数すう据すえ处理操作そうさ的てき算さん术逻辑单元もと、乘法じょうほう器き、寄よせ存そん器き和わ总线。它与控ひかえ制せい单元一起かずき组成中央ちゅうおう处理器き（CPU）。^[1]通つう过使用しよう数かず据すえ选择器き连接多た于一个的数据通路，可か以创建けん更さら大だい的てき数すう据すえ通路つうろ。

在ざい1990年代ねんだい后きさき期き，在ざい可か重じゅう构数かず据すえ通路つうろ领域（可か以在运行时使用しようFPGA重じゅう复使用しよう的てき数すう据すえ通路つうろ）方面ほうめん的てき研究けんきゅう不断ふだん增ぞう多た，因いん为这样的设计可か以在提ひさげ升ます处理效率こうりつ的てき同どう时节省しょう电能。^[2]

参考さんこう文献ぶんけん[编辑]

^ Null, Linda; Lobur, Julia. The Essentials of Computer Organization and Architecture. Jones & Bartlett Learning. 2006: 2016 [2020-02-14]. ISBN 978-0-7637-3769-6. （原始げんし内容ないよう存そん档于2020-07-31）. All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks.
^ J. R. Hauser and J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, FCCM’97, 1997, pp. 12–21. （页面存そん档备份，存そん于互联网档案あん馆）

[NullLobur2006-1] Null, Linda; Lobur, Julia. The Essentials of Computer Organization and Architecture. Jones & Bartlett Learning. 2006: 2016 [2020-02-14]. ISBN 978-0-7637-3769-6. （原始げんし内容ないよう存そん档于2020-07-31）. All computers have a CPU that can be divided into two pieces. The first is the datapath, which is a network of storage units (registers) and arithmetic and logic units... connected by buses... where the timing is controlled by clocks.

[2] J. R. Hauser and J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, FCCM’97, 1997, pp. 12–21. （页面存そん档备份，存そん于互联网档案あん馆）

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